Sehyeon Chung

According to our database, Sehyeon Chung authored at least 6 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

Standard Cell Layout Generator Amenable to Design Technology Co-Optimization in Advanced Process Nodes.

Handong Cho, Hyunbae Seo, Sehyeon Chung, Kyu-Myung Choi, Taewhan Kim

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin Accessibility.

Jooyeon Jeong, Sehyeon Chung, Kyeongrok Jo, Taewhan Kim

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

ECO routing based on network flow method.

Sehyeon Chung, Taewhan Kim

Integr., 2022

Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs.

Suwan Kim, Sehyeon Chung, Taewhan Kim, Heechun Park

Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis.

Sehyeon Chung, Jooyeon Jeong, Taewhan Kim

Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

2021

Analyses of Power Staple Inserting Methodologies for Mitigating IR-Drops.

Jaejoon Yoon, Sehyeon Chung, Taewhan Kim

Proceedings of the 18th International SoC Design Conference, 2021