Seetal Potluri

According to our database, Seetal Potluri authored at least 35 papers between 2011 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

SoK: Model Reverse Engineering Threats for Neural Network Hardware.

Seetal Potluri, Farinaz Koushanfar

IACR Cryptol. ePrint Arch., 2024

2023

SeqL+: Secure Scan-Obfuscation With Theoretical and Empirical Validation.

Seetal Potluri, Shamik Kundu, Akash Kumar, Kanad Basu, Aydin Aysu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

Scalable Scan-Chain-Based Extraction of Neural Network Models.

Shui Jiang, Seetal Potluri, Tsung-Yi Ho

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

RevEAL: Single-Trace Side-Channel Leakage of the SEAL Homomorphic Encryption Library.

Furkan Aydin, Emre Karabulut, Seetal Potluri, Erdem Alkim, Aydin Aysu

IACR Cryptol. ePrint Arch., 2022

Towards AI-Enabled Hardware Security: Challenges and Opportunities.

Hossein Sayadi, Mehrdad Aliasgari, Furkan Aydin, Seetal Potluri, Aydin Aysu, Jack Edmonds, Sara Tehranipoor

Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

PR Crisis: Analyzing and Fixing Partial Reconfiguration in Multi-Tenant Cloud FPGAs.

Emre Karabulut, Chandu Yuvarajappa, Mohammed Iliyas Shaik, Seetal Potluri, Amro Awad, Aydin Aysu

Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security, 2022

2021

2Deep: Enhancing Side-Channel Attacks on Lattice-Based Key-Exchange via 2-D Deep Learning.

Priyank Kashyap, Furkan Aydin, Seetal Potluri, Paul D. Franzon, Aydin Aysu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Stealing Neural Network Models through the Scan Chain: A New Threat for ML Hardware.

Seetal Potluri, Aydin Aysu

IACR Cryptol. ePrint Arch., 2021

iTimed: Cache Attacks on the Apple A10 Fusion SoC.

Gregor Haas, Seetal Potluri, Aydin Aysu

IACR Cryptol. ePrint Arch., 2021

2020

Security of Microfluidic Biochip: Practical Attacks and Countermeasures.

Huili Chen, Seetal Potluri, Farinaz Koushanfar

ACM Trans. Design Autom. Electr. Syst., 2020

Scalable pseudo-exhaustive methodology for testing and diagnosis in flow-based microfluidic biochips.

Gokulkrishnan Vadakkeveedu, Kamakoti Veezhinathan, Nitin Chandrachoodan, Seetal Potluri

IET Comput. Digit. Tech., 2020

DeePar-SCA: Breaking Parallel Architectures of Lattice Cryptography via Learning Based Side-Channel Attacks.

Furkan Aydin, Priyank Kashyap, Seetal Potluri, Paul D. Franzon, Aydin Aysu

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020

FlowTrojan: Insertion and Detection of Hardware Trojans on Flow-Based Microfluidic Biochips.

Huili Chen, Seetal Potluri, Farinaz Koushanfar

Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020

SeqL: Secure Scan-Locking for IP Protection.

Seetal Potluri, Aydin Aysu, Akash Kumar

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Efficacy of Satisfiability-Based Attacks in the Presence of Circuit Reverse-Engineering Errors.

Qinhan Tan, Seetal Potluri, Aydin Aysu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Machine Learning and Hardware security: Challenges and Opportunities -Invited Talk-.

Francesco Regazzoni, Shivam Bhasin, Amir Alipour, Ihab Alshaer, Furkan Aydin, Aydin Aysu, Vincent Beroulle, Giorgio Di Natale, Paul D. Franzon, David Hély, Naofumi Homma, Akira Ito, Dirmanto Jap, Priyank Kashyap, Ilia Polian, Seetal Potluri, Rei Ueno, Elena-Ioana Vatajelu, Ville Yli-Mäyry

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

2019

Design-for-Testability of On-Chip Control in mVLSI Biochips.

Seetal Potluri, Paul Pop, Jan Madsen

IEEE Des. Test, 2019

2018

MLTimer: Leakage Power Minimization in Digital Circuits Using Machine Learning and Adaptive Lazy Timing Analysis.

Patanjali SLPSK, Milan Patnaik, Seetal Potluri, V. Kamakoti

J. Low Power Electron., 2018

2017

Optimal Don't Care Filling for Minimizing Peak Toggles During At-Speed Stuck-At Testing.

Satya Trinadh Adireddy, Seetal Potluri, Ch. Sobhan Babu, Veezhinathan Kamakoti, Shiv Govind Singh

ACM Trans. Design Autom. Electr. Syst., 2017

BioChipWork: Reverse Engineering of Microfluidic Biochips.

Huili Chen, Seetal Potluri, Farinaz Koushanfar

Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

A scalable pseudo-exhaustive search for fault diagnosis in microfluidic biochips.

Gokulkrishnan Vadakkeveedu, V. Kamakoti, Nitin Chandrachoodan, Seetal Potluri

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Synthesis of on-chip control circuits for mVLSI biochips.

Seetal Potluri, Alexander Schneider, Martin Horslev-Petersen, Paul Pop, Jan Madsen

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Cell-Aware ATPG to Improve Defect Coverage for FPGA IPs and Next Generation Zynq® MPSoCs.

Seetal Potluri, Aaron Mathew, Rambabu Nerukonda, Ismed Hartanto, Shahin Toutounchi

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Power Consumption versus Hardware Security: Feasibility Study of Differential Power Attack on Linear Feedback Shift Register Based Stream Ciphers and Its Countermeasures.

Sanjay Burman, Seetal Potluri, Debdeep Mukhopadhyay, Kamakoti Veezhinathan

J. Low Power Electron., 2016

Component fault localization using switching current measurements.

Seetal Potluri, Satya Trinadh, Siddhant Saraf, Kamakoti Veezhinathan

Proceedings of the 21th IEEE European Test Symposium, 2016

Architecture synthesis for cost-constrained fault-tolerant flow-based biochips.

Morten Chabert Eskesen, Paul Pop, Seetal Potluri

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

DFT Assisted Techniques for Peak Launch-to-Capture Power Reduction during Launch-On-Shift At-Speed Testing.

Seetal Potluri, Satya Trinadh, Ch. Sobhan Babu, V. Kamakoti, Nitin Chandrachoodan

ACM Trans. Design Autom. Electr. Syst., 2015

DP-fill: a dynamic programming approach to X-filling for minimizing peak test power in scan tests.

Satya Trinadh, Ch. Sobhan Babu, Shiv Govind Singh, Seetal Potluri, V. Kamakoti

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

XStat: Statistical <i>X</i>-Filling Algorithm for Peak Capture Power Reduction in Scan Tests.

Satya Trinadh, Seetal Potluri, Shankar Balachandran, Ch. Sobhan Babu, V. Kamakoti

J. Low Power Electron., 2014

2013

An Efficient Heuristic for Peak Capture Power Minimization During Scan-Based Test.

Satya Trinadh, Seetal Potluri, Ch. Sobhan Babu, V. Kamakoti

J. Low Power Electron., 2013

LPScan: An algorithm for supply scaling and switching activity minimization during test.

Seetal Potluri, Satya Trinadh Adireddy, Chidhambaranathan Rajamanikkam, Shankar Balachandran

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

PinPoint: An algorithm for enhancing diagnostic resolution using capture cycle power information.

Seetal Potluri, Satya Trinadh, Roopashree Baskaran, Nitin Chandrachoodan, V. Kamakoti

Proceedings of the 18th IEEE European Test Symposium, 2013

2012

Interconnect Aware Test Power Reduction.

Seetal Potluri, Nitin Chandrachoodan, V. Kamakoti

J. Low Power Electron., 2012

Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs.

Rama Kumar Pasumarthi, V. R. Devanathan, V. Visvanathan, Seetal Potluri, V. Kamakoti

J. Low Power Electron., 2012

2011

Post-Synthesis Circuit Techniques for Runtime Leakage Reduction.

Seetal Potluri, Nitin Chandrachoodan, V. Kamakoti

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011