Seda Ogrenci Memik

Román Hermida

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018

Machine Learning-Based Temperature Prediction for Runtime Thermal Management Across System Components.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2018

Minimizing Thermal Variation in Heterogeneous HPC Systems with FPGA Nodes.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE International Conference on Computer Design, 2018

2017

End-to-End Analysis of Integration for Thermocouple-Based Sensors Into 3-D ICs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

A content addressable memory with multi-Vdd scheme for low power tunable operation.

[BibT_eX]

[DOI]

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Cell-to-array thermal-aware analysis of stacked RRAM.

[BibT_eX]

[DOI]

Yingyi Luo

Jie Gu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBench.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Adaptive Thermal Management for 3D ICs with Stacked DRAM Caches.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

2016

A Partial Carry-Save On-the-Fly Correction Multispeculative Multiplier.

[BibT_eX]

[DOI]

Román Hermida

IEEE Trans. Computers, 2016

Lazy Pipelines: Enhancing quality in approximate computing.

[BibT_eX]

[DOI]

Georgios Tziantzioulis

Srinivasan Parthasarathy

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

On-chip integration of thermoelectric energy harvesting in 3D ICs.

[BibT_eX]

[DOI]

Dawei Li

Lawrence J. Henschen

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Minimizing Thermal Variation Across System Components.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium, 2015

A methodology for power characterization of associative memories.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

User-specific skin temperature-aware DVFS for smartphones.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

b-HiVE: a bit-level history-based error model with value correlation for voltage-scaled integer and floating point units.

[BibT_eX]

[DOI]

Georgios Tziantzioulis

Srinivasan Parthasarathy

Proceedings of the 52nd Annual Design Automation Conference, 2015

Edge importance identification for energy efficient graph processing.

[BibT_eX]

[DOI]

S. M. Faisal

Georgios Tziantzioulis

Ali Murat Gok

Nikolaos Hardavellas

Srinivasan Parthasarathy

Proceedings of the 2015 IEEE International Conference on Big Data (IEEE BigData 2015), Santa Clara, CA, USA, October 29, 2015

2014

Improving circuit performance with multispeculative additive trees in high-level synthesis.

[BibT_eX]

[DOI]

Microelectron. J., 2014

2013

Theory and Analysis for Optimization of On-Chip Thermoelectric Cooling Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths.

[BibT_eX]

[DOI]

Integr., 2013

Exploring super-resolution implementations across multiple platforms.

[BibT_eX]

[DOI]

Brian Leung

EURASIP J. Adv. Signal Process., 2013

Integrating thermocouple sensors into 3D ICs.

[BibT_eX]

[DOI]

Dawei Li

Ji-Hoon Kim

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Exploring the energy efficiency of Multispeculative Adders.

[BibT_eX]

[DOI]

Román Hermida

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Multispeculative additive trees in high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Multispeculative Addition Applied to Datapath Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011

A Distributed Controller for Managing Speculative Functional Units in High Level Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

A Comprehensive Tapered buffer optimization algorithm for unified design metrics.

[BibT_eX]

[DOI]

Song Liu

Yehea I. Ismail

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Hardware/software techniques for DRAM thermal management.

[BibT_eX]

[DOI]

Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

Power optimization in heterogenous datapaths.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2010

A Fast Heuristic Algorithm for Multidomain Clock Skew Scheduling.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

SACTA: A Self-Adjusting Clock Tree Architecture for Adapting to Thermal-Induced Delay Variation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

An Approach for Adaptive DRAM Temperature and Power Management.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

Placement and Floorplanning in Dynamically Reconfigurable FPGAs.

[BibT_eX]

[DOI]

Alessio Montone

Donatella Sciuto

ACM Trans. Reconfigurable Technol. Syst., 2010

A revisit to the primal-dual based clock skew scheduling algorithm.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

An Interior Point Optimization Solver for Real Time Inter-frame Collision Detection: Exploring Resource-Accuracy-Platform Tradeoffs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Optimization of an on-chip active cooling system based on thin-film thermoelectric coolers.

[BibT_eX]

[DOI]

Matthew Grayson

Proceedings of the Design, Automation and Test in Europe, 2010

Inversed Temperature Dependence aware clock skew scheduling for sequential circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Optimization of the bias current network for accurate on-chip thermal monitoring.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Using Speculative Functional Units in high level synthesis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

A framework for optimizing thermoelectric active cooling systems.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

2009

An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-Dimensional Reconfigurable Architectures.

[BibT_eX]

[DOI]

Francesco Redaelli

Int. J. Reconfigurable Comput., 2009

FPGA Implementation of the Interior-Point Algorithm with Applications to Collision Detection.

[BibT_eX]

[DOI]

Chih-Hung Wu

Sanjay Mehrotra

Proceedings of the FCCM 2009, 2009

2008

A high-level clustering algorithm targeting dual Vdd FPGAs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2008

Optimizing Thermal Sensor Allocation for Microprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Presynthesis Area Estimation of Reconfigurable Streaming Accelerators.

[BibT_eX]

[DOI]

Nikolaos Bellas

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

EBOARST: An Efficient Edge-Based Obstacle-Avoiding Rectilinear Steiner Tree Construction Algorithm.

[BibT_eX]

[DOI]

Hai Zhou

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Thermal monitoring mechanisms for chip multiprocessors.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2008

A Reconfiguration-Aware Floorplacer for FPGAs.

[BibT_eX]

[DOI]

Alessio Montone

Francesco Redaelli

Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

An O(nlogn) edge-based algorithm for obstacle-avoiding rectilinear steiner tree construction.

[BibT_eX]

[DOI]

Hai Zhou

Proceedings of the 2008 International Symposium on Physical Design, 2008

Towards an "early neural circuit simulator": A FPGA implementation of processing in the rat whisker system.

[BibT_eX]

[DOI]

Brian Leung

Yan Pan

Christopher L. Schroeder

Mitra J. Z. Hartmann

Proceedings of the FPL 2008, 2008

Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

Automated design of self-adjusting pipelines.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

A power and temperature aware DRAM architecture.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2007

Managing Reconfigurable Resources in Heterogeneous Cores Using Portable Pre-Synthesized Templates.

[BibT_eX]

[DOI]

Matteo Giani

Proceedings of the International Symposium on System-on-Chip, 2007

A novel SoC design methodology combining adaptive software and reconfigurable hardware.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Early planning for clock skew scheduling during register binding.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

A self-adjusting clock tree architecture to cope with temperature variations.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Self-heating-aware optimal wire sizing under Elmore delay model.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

An Integrated Approach to Thermal Management in High-Level Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Fine-grain thermal profiling and sensor insertion for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Thermal-induced leakage power optimization by redundant resource allocation.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Thermal sensor allocation and placement for reconfigurable systems.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Physical aware frequency selection for dynamic thermal management in multi-core systems.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Combining hardware reconfiguration and adaptive computation for a novel SoC design methodology.

[BibT_eX]

[DOI]

Vincenzo Rana

Donatella Sciuto

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

Pre-Synthesis Area Estimation of Reconfigurable Streaming Accelerators.

[BibT_eX]

[DOI]

Nikolaos Bellas

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Power Optimization Techniques for SRAM-Based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Adaptive Metrics for System-Level Functional Partitioning.

[BibT_eX]

[DOI]

Giovanni Agosta

Proceedings of the Forum on specification and Design Languages, 2006

Pre-synthesis Queue Size Estimation of Streaming Data Flow Graphs.

[BibT_eX]

[DOI]

Nikolaos Bellas

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

A Sensor Distribution Algorithm for FPGAs with Minimal Dynamic Reconfiguration Overhead.

[BibT_eX]

Proceedings of the 2006 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2006

Systematic temperature sensor allocation and placement for microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

2005

A scheduling algorithm for optimization and early planning in high-level synthesis.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2005

On effective slack management in postscheduling phase.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Early Quality Assessment for Low Power Behavioral Synthesis.

[BibT_eX]

[DOI]

Eren Kursun

J. Low Power Electron., 2005

Peak temperature control and leakage reduction during binding in high level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

A low power FPGA routing architecture.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Quick Reconfiguration in Clustered Micro-Sequencer.

[BibT_eX]

[DOI]

Roozbeh Jafari

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Fine-grain leakage optimization in SRAM based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Real-Time Feature Extraction for High Speed Networks.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Hierarchical LUT structures for leakage power reduction (abstract only).

[BibT_eX]

[DOI]

Debasish Das

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Temperature-aware resource allocation and binding in high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

Evaluation of dual VDD fabrics for low power FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Resource sharing in pipelined CDFG synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Routability-Driven Packing: Metrics And Algorithms For Cluster-Based FPGAs.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2004

Power-Driven Design Partitioning.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 2004

Power Management for FPGAs: Power-Driven Design Partitioning.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

2003

Analysis and FPGA Implementation of Image Restoration under Resource Constraints.

[BibT_eX]

[DOI]

Aggelos K. Katsaggelos

IEEE Trans. Computers, 2003

Achieving Design Closure Through Delay Relaxation Parameter.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Global resource sharing for synthesis of control data flow graphs on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

2002

Instruction generation for hybrid reconfigurable systems.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2002

Early evaluation techniques for low power binding.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Accelerated SAT-based Scheduling of Control/Data Flow Graphs.

[BibT_eX]

[DOI]

Farzan Fallah

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic.

[BibT_eX]

[DOI]

William H. Mangione-Smith

Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

2001

Fast floorplanning for effective prediction and construction.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

A Super-Scheduler for Embedded Reconfigurable Systems.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Instruction Generation for Hybrid Reconfigurable Systems.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures.

[BibT_eX]

[DOI]

Kia Bazargan

Seda Ogrenci

Proceedings of the 38th Design Automation Conference, 2001

RPack: routability-driven packing for cluster-based FPGAs.

[BibT_eX]

[DOI]

Elaheh Bozorgzadeh