Modélisation, Conception Système d'Architectures Hétérogènes pour les Applications Embarquées : Eléments d'amélioration de l'efficacité énergétique des systèmes sur puce de silicium. (Modelling, Design of Heterogenous architectures for embedded Applications / Modelling, Design of Heterogenous architectures for embedded Applications : Refinement parts about power efficiency of silicon chips systems).

[BibT_eX]

[DOI]

Sébastien Bilavarn

, 2018

2017

Efficiency modeling and exploration of 64-bit ARM compute nodes for exascale.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2017

2016

Effectiveness of power strategies for video applications: a practical study.

[BibT_eX]

[DOI]

Sébastien Bilavarn

Jabran Khan

Cécile Belleudy

Muhammad Khurram Bhatti

J. Real Time Image Process., 2016

Power Modeling and Exploration of Dynamic and Partially Reconfigurable Systems.

[BibT_eX]

[DOI]

J. Low Power Electron., 2016

Efficiency Modeling and Analysis of 64-bit ARM Clusters for HPC.

[BibT_eX]

[DOI]

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015

FoRTReSS: a flow for design space exploration of partially reconfigurable systems.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2015

An energy-aware scheduler for dynamically reconfigurable multi-core systems.

[BibT_eX]

[DOI]

Robin Bonamy

Sébastien Bilavarn

Fabrice Muller

Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

HLS based design of a mixed architecture for H.264/AVC CAVLD.

[BibT_eX]

[DOI]

Taheni Damak

Sébastien Bilavarn

Nouri Masmoudi

Proceedings of the 12th IEEE International Multi-Conference on Systems, Signals & Devices, 2015

2014

Power consumption models for the use of dynamic and partial reconfiguration.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2014

2013

Energy Analysis of a Real-time Multiprocessor Control of Idle States.

[BibT_eX]

Jabran Khan

Sébastien Bilavarn

Muhammad Khurram Bhatti

Cécile Belleudy

Proceedings of the PECCS 2013, 2013

2012

Power consumption model for partial and dynamic reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Impact of operating points on DVFS power management.

[BibT_eX]

[DOI]

Jabran Khan

Sébastien Bilavarn

Cécile Belleudy

Proceedings of the 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2012

Open-People: Open Power and Energy Optimization PLatform and Estimator.

[BibT_eX]

[DOI]

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011

Parallelism Level Impact on Energy Consumption in Reconfigurable Devices.

[BibT_eX]

[DOI]

SIGARCH Comput. Archit. News, 2011

AADL Extension to Model Classical FPGA and FPGA Embedded within a SoC.

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2011

Exploitation of the EDF Scheduling in the Wireless Sensors Networks.

[BibT_eX]

[DOI]

Rym Chéour

Sébastien Bilavarn

Mohamed Abid

Int. J. Meas. Technol. Instrum. Eng., 2011

Towards a power and energy efficient use of partial dynamic reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Embedded operating systems energy overhead.

[BibT_eX]

[DOI]

Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

A Video Monitoring Application forWireless Sensor Networks using IEEE 802.15.4.

[BibT_eX]

[DOI]

Sébastien Bilavarn

Andrea Castagnetti

Laurent Rodriguez

Proceedings of the ARCS 2011, 2011

2010

Implantation d'un décodeur H.264 sur plateforme multiprocesseur avec gestion énergétique.

[BibT_eX]

[DOI]

Tech. Sci. Informatiques, 2010

Power Consumption Modeling for DVFS Exploitation.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009

UML for Modelling and Performance Estimation of Embedded Systems.

[BibT_eX]

[DOI]

J. Object Technol., 2009

UML2.0 Profiles for Embedded Systems and Systems On a Chip (SOCs).

[BibT_eX]

[DOI]

J. Object Technol., 2009

2008

UML profile for estimating application Worst Case Execution Time on System-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008

Embedded Multicore Implementation of a H.264 Decoder with Power Management Considerations.

[BibT_eX]

[DOI]

Anne-Marie Fouilliart

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2006

Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

EPICURE: A partitioning and co-design framework for reconfigurable computing.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2006

2005

Processor Enhancements for Media Streaming Applications.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2005

2004

Reconfigurable coprocessor for media streaming.

[BibT_eX]

[DOI]

Sébastien Bilavarn

Eric Debes

Proceedings of the 2004 IEEE International Conference on Multimedia and Expo, 2004

2003

Fast prototyping of reconfigurable architectures from a C program.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

An estimation and exploration methodology from system-level specifications: application to FPGAs.

[BibT_eX]

[DOI]

Sébastien Bilavarn

Guy Gogniat

Jean Luc Philippe

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

2002

Exploration Architecturale au Niveau Comportemental - Application aux FPGAs. (Architectural Exploration in behavioral level - Application to FPGAs).

[BibT_eX]

[DOI]

Sébastien Bilavarn

PhD thesis, 2002

2000

Area time power estimation for FPGA based designs at a behavioral level.

[BibT_eX]

[DOI]

Sébastien Bilavarn

Guy Gogniat

Jean Luc Philippe

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

Sébastien Bilavarn

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