Sebastian Siegfried Prebeck

According to our database1, Sebastian Siegfried Prebeck authored at least 16 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
HW-Acceleration for Edge-AI.
PhD thesis, 2024

An Automated Exhaustive Fault Analysis Technique guided by Processor Formal Verification Methods.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

2023
Generator IP-reuse and Automated Infrastructure Generation for Model-based Full-Chip Generation.
Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2023

Parallel Golomb-Rice Decoder with 8-bit Unary Decoding for Weight Compression in TinyML Applications.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

Bits, Flips and RISCs.
Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

G-QED: Generalized QED Pre-silicon Verification beyond Non-Interfering Hardware Accelerators.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Early RTL delay prediction using neural networks.
Microprocess. Microsystems, October, 2022

A Smart HW-Accelerator for Non-uniform Linear Interpolation of ML-Activation Functions.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022

A Scalable, Configurable and Programmable Vector Dot-Product Unit for Edge AI.
Proceedings of the Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2022

2021
Aspect-Oriented Design Automation with Model Transformation.
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

Transformative Hardware Design Following the Model-Driven Architecture Vision.
Proceedings of the VLSI-SoC: Technology Advancement on SoC Design, 2021

RTL Delay Prediction Using Neural Networks.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2021, Oslo, 2021

Towards Fault Simulation at Mixed Register-Transfer/Gate-Level Models.
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

ISA Modeling with Trace Notation for Context Free Property Generation.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021


2020
Optimized HW/FW Generation from an Abstract Register Interface Model.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020


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