Sebastian Siegel

According to our database, Sebastian Siegel authored at least 18 papers between 2004 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

IMSSA: Deploying modern state-space models on memristive in-memory compute hardware.

Sebastian Siegel, Ming-Jay Yang, John Paul Strachan

CoRR, 2024

Analog In-Memory Computing Attention Mechanism for Fast and Energy-Efficient Large Language Models.

Nathan Leroux, Paul-Philipp Manea, Chirag Sudarshan, Jan Finkbeiner, Sebastian Siegel, John Paul Strachan, Emre Neftci

CoRR, 2024

Synaptogen: A cross-domain generative device model for large-scale neuromorphic circuit design.

Tyler Hennen, Leon Brackmann, Tobias Ziegler, Sebastian Siegel, Stephan Menzel, Rainer Waser, Dirk J. Wouters, Daniel Bedau

CoRR, 2024

The Ouroboros of Memristors: Neural Networks Facilitating Memristor Programming.

Zhenming Yu, Ming-Jay Yang, Jan Finkbeiner, Sebastian Siegel, John Paul Strachan, Emre Neftci

Proceedings of the 6th IEEE International Conference on AI Circuits and Systems, 2024

2023

Sequence learning in a spiking neuronal network with memristive synapses.

Younes Bouhadjar, Sebastian Siegel, Tom Tetzlaff, Markus Diesmann, Rainer Waser, Dirk J. Wouters

Neuromorph. Comput. Eng., September, 2023

System model of neuromorphic sequence learning on a memristive crossbar array.

Sebastian Siegel, Younes Bouhadjar, Tom Tetzlaff, Rainer Waser, Regina Dittmann, Dirk J. Wouters

Neuromorph. Comput. Eng., June, 2023

Demonstration of neuromorphic sequence learning on a memristive array.

Sebastian Siegel, Tobias Ziegler, Younes Bouhadjar, Tom Tetzlaff, Rainer Waser, Regina Dittmann, Dirk J. Wouters

Proceedings of the Neuro-Inspired Computational Elements Conference, 2023

Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories.

Felix Staudigl, Mohammed Hossein, Tobias Ziegler, Hazem Al Indari, Rebecca Pelke, Sebastian Siegel, Dirk J. Wouters, Dominik Sisejkovic, Jan Moritz Joseph, Rainer Leupers

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2023

2007

Abbildungsverfahren zur effizienten Implementierung rechenintensiver Algorithmen auf Prozessorarrays.

Sebastian Siegel

PhD thesis, 2007

Massively Parallel Processor Architectures: A Co-design Approach.

Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier

Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

2006

Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels.

Sebastian Siegel, Rainer Schaffer, Renate Merker

Proceedings of the Fifth International Conference on Parallel Computing in Electrical Engineering (PARELEC 2006), 2006

Efficient Realization of Data Dependencies in Algorithm Partitioning Under Resource Constraints.

Sebastian Siegel, Renate Merker

Proceedings of the Euro-Par 2006, Parallel Processing, 12th International Euro-Par Conference, Dresden, Germany, August 28, 2006

Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy.

Sebastian Siegel, Renate Merker

Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005

Co-Design of Massively Parallel Embedded Processor Architectures.

Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Ménard, Olivier Sentieys

Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

Optimization of Reconfiguration Overhead by Algorithmic Transformations and Hardware Matching.

Markus Rullmann, Sebastian Siegel, Renate Merker

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

2004

Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays.

Sebastian Siegel, Renate Merker

Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

A Parallel Hardware-Software System for Signal Processing Algorithms.

Mathias Kortke, Jan Müller, Rainer Schaffer, Sebastian Siegel, Renate Merker, Jürgen Kelber

Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

Optimized Data-Reuse in Processor Arrays.

Sebastian Siegel, Renate Merker

Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004