Sebastian Höppner
Orcid: 0000-0002-9938-2736
According to our database1,
Sebastian Höppner
authored at least 61 papers
between 2010 and 2023.
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Bibliography
2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI.
Proceedings of the 20th International SoC Design Conference, 2023
A 12-ADC 25-Core Smart MPSoC Using ABB in 22FDX for 77GHz MIMO Radars at 52.6mW Average Power.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 16-Channel Fully Configurable Neural SoC With 1.52 $\mu$W/Ch Signal Acquisition, 2.79 $\mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI.
IEEE Trans. Biomed. Circuits Syst., 2022
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022
A Single Battery Supply Power Concept for a Neuro Recording and Flexible Processing Chain in 22 nm.
Proceedings of the IEEE Nordic Circuits and Systems Conference, NorCAS 2022, Oslo, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
ZEN: A flexible energy-efficient hardware classifier exploiting temporal sparsity in ECG data.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
Hardware Acceleration of EEG-Based Emotion Classification Systems: A Comprehensive Survey.
IEEE Trans. Biomed. Circuits Syst., 2021
Comparing Loihi with a SpiNNaker 2 prototype on low-latency keyword spotting and adaptive robotic control.
Neuromorph. Comput. Eng., 2021
The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing.
CoRR, 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IECON 2021, 2021
2020
Mean Field Approach for Configuring Population Dynamics on a Biohybrid Neuromorphic System.
J. Signal Process. Syst., 2020
Adaptive Body Bias Aware Implementation for Ultra-Low-Voltage Designs in 22FDX Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Low-Power Low-Latency Keyword Spotting and Adaptive Control with a SpiNNaker 2 Prototype and Comparison with Loihi.
CoRR, 2020
A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM.
Proceedings of the 2020 IEEE Symposium in Low-Power and High-Speed Chips, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Biomed. Circuits Syst., 2019
SpiNNaker 2: A 10 Million Core Processor System for Brain Simulation and Machine Learning.
CoRR, 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A Fast Lock-In Ultra Low-Voltage ADPLL Clock Generator with Adaptive Body Biasing in 22nm FDSOI Technology.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Hard Real-Time Capable OPC UA Server as Hardware Peripheral for Single Chip IoT Systems.
Proceedings of the 24th IEEE International Conference on Emerging Technologies and Factory Automation, 2019
How to Achieve World-Leading Energy Efficiency using 22FDX with Adaptive Body Biasing on an Arm Cortex-M4 IoT SoC.
Proceedings of the 49th European Solid-State Device Research Conference, 2019
2018
Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip.
Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018
2017
Application-specific architectures for energy-efficient database query processing and optimization.
Microprocess. Microsystems, 2017
Exploration of FPGA architectures for tight coupled accelerators in a 22nm FDSOI technology.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor Circuits.
IEEE Trans. Biomed. Circuits Syst., 2016
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS.
IEEE J. Solid State Circuits, 2015
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Switched-Capacitor Realization of Presynaptic Short-Term-Plasticity and Stop-Learning Synapses in 28 nm CMOS.
CoRR, 2014
A 10 bit 16 MS/s redundant SAR ADC with flexible window function for a digitally controlled DC-DC converter in 28 nm CMOS.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014
10.7 A 105GOPS 36mm<sup>2</sup> heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
2012
On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links.
Int. J. Embed. Real Time Commun. Syst., 2012
A 335Mb/s 3.9mm<sup>2</sup> 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
Proceedings of the 2011 International Symposium on System on Chip, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010