Sebastian Cieslak

According to our database, Sebastian Cieslak authored at least 2 papers in 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2019

Design and Verification Environment for RISC-V Processor Cores.

Adrian Oleksiak, Sebastian Cieslak, Krzysztof Marcinek, Witold A. Pleskacz

Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019

Retargeting the MIPS-II CPU Core to the RISC-V Architecture.

Sebastian Cieslak, Adrian Oleksiak, Krzysztof Marcinek, Witold A. Pleskacz

Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019