Sebastià A. Bota
Orcid: 0000-0002-7653-0740
According to our database1,
Sebastià A. Bota
authored at least 64 papers
between 1996 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results.
CoRR, 2024
A 164-dBΩ Transimpedance Amplifier for Monolithic CMOS-MEMS Oscillators in Biosensing Applications.
IEEE Access, 2024
2023
Proceedings of the 38th Conference on Design of Circuits and Integrated Systems, 2023
2022
Fully Integrated Front-End CMOS-MEMS Transducer for Low-Cost Real-Time Breath Monitoring.
Proceedings of the 2022 IEEE Sensors, Dallas, TX, USA, October 30 - Nov. 2, 2022, 2022
Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022
2021
2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Selection of SRAM Cells to improve Reliable PUF implementation using Cell Mismatch Metric.
Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020
2019
IEEE Trans. Emerg. Top. Comput., 2019
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019
2018
Sensors, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Soft error rate comparison of 6T and 8T SRAM ICs using mono-energetic proton and neutron irradiation sources.
Microelectron. Reliab., 2017
Statistical characterization and modeling of random telegraph noise effects in 65nm SRAMs cells.
Proceedings of the 14th International Conference on Synthesis, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017
2016
An affordable experimental technique for SRAM write margin characterization for nanometer CMOS technologies.
Microelectron. Reliab., 2016
Electrostatically actuated microbeam resonators as chaotic signal generators: A practical perspective.
Commun. Nonlinear Sci. Numer. Simul., 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
2015
Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell.
Proceedings of the 16th Latin-American Test Symposium, 2015
2014
Sensitization Input Vector Impact on Propagation Delay for Nanometer CMOS ICs: Analysis and Solutions.
IEEE Trans. Very Large Scale Integr. Syst., 2014
Microelectron. Reliab., 2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Word-line power supply selector for stability improvement of embedded SRAMs in high reliability applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Alternate characterization technique for static random-access memory static noise margin determination.
Int. J. Circuit Theory Appl., 2013
Proceedings of the 14th Latin American Test Workshop, 2013
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
2012
Resistive bridge defect detection enhancement under parameter variations combining Low V<sub>DD</sub> and body bias in a delay based test.
Microelectron. Reliab., 2012
2011
Microelectron. Reliab., 2011
An efficient and scalable STA tool with direct path estimation and exhaustive sensitization vector exploration for optimal delay computation.
Proceedings of the Design, Automation and Test in Europe, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
2010
IEEE Trans. Instrum. Meas., 2010
Design Hardening of Nanometer SRAMs Through Transistor Width Modulation and Multi-Vt Combination.
IEEE Trans. Circuits Syst. II Express Briefs, 2010
Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Proceedings of the 27th IEEE VLSI Test Symposium, 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
2008
2007
Heavy Ion Test Results in a CMOS triple Voting Register for a High-Energy Physics Experiment.
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Dynamic critical resistance: a timing-based critical resistance model for statistical delay testing of nanometer ICs.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
2006
Force-balance interface circuit based on floating MOSFET capacitors for micro-machined capacitive accelerometers.
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Proceedings of the International Joint Conference on Neural Networks, 2006
2005
Proceedings of the Integrated Circuit and System Design, 2005
A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Design, 2005
2004
IEEE Trans. Instrum. Meas., 2004
Within Die Thermal Gradient Impact on Clock-Skew: A New Type of Delay-Fault Mechanism.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
A mixed-mode temperature control circuit for gas sensors.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
On-line Monitoring Capabilities of Oscillation Test Techniques: Results Demonstration in an OTA.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004
2002
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, Lausanne, Switzerland, September 30, 2002
2001
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001
Proceedings of 8th IEEE International Conference on Emerging Technologies and Factory Automation, 2001
1999
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
1998
IEEE Trans. Instrum. Meas., 1998
1996
Implementation and design of a new model of neural network with application to typographical character recognition.
Proceedings of the Proceedings 1996 International Conference on Image Processing, 1996