Seamus Cawley
According to our database1,
Seamus Cawley
authored at least 16 papers
between 2009 and 2018.
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Bibliography
2018
Vicilogic 2.0: Online Learning and Prototyping of Digital Systems Using PYNQ-Z1/-Z2 SoC.
Proceedings of the 2018 International Symposium on Rapid System Prototyping, 2018
2014
Exploring Neural Principles with Si elegans, a Neuromimetic Representation of the Nematode Caenorhabditis elegans.
Proceedings of the 2nd International Congress on Neurotechnology, 2014
The Si elegans Project - The Challenges and Prospects of Emulating Caenorhabditis elegans.
Proceedings of the Biomimetic and Biohybrid Systems - Third International Conference, 2014
2013
Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations.
IEEE Trans. Parallel Distributed Syst., 2013
Fixed latency on-chip interconnect for hardware spiking neural network architectures.
Parallel Comput., 2013
Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network.
Neural Process. Lett., 2013
2012
ACM Trans. Reconfigurable Technol. Syst., 2012
Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers.
Neural Networks, 2012
Hierarchical Network-on-Chip and Traffic Compression for Spiking Neural Network Implementations.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012
2011
Genet. Program. Evolvable Mach., 2011
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011
Addressing the Hardware Resource Requirements of Network-on-chip based Neural Architectures.
Proceedings of the NCTA 2011, 2011
Adaptive Routing Strategies for Large Scale Spiking Neural Network Hardware Implementations.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2011, 2011
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
2010
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010
2009
A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks.
Int. J. Reconfigurable Comput., 2009