Se-Joong Lee

According to our database1, Se-Joong Lee authored at least 20 papers between 2000 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2009
81.6 GOPS Object Recognition Processor Based on a Memory-Centric NoC.
IEEE Trans. Very Large Scale Integr. Syst., 2009

2006
Low-power network-on-chip for high-performance SoC design.
IEEE Trans. Very Large Scale Integr. Syst., 2006

A network-on-chip with 3Gbps/wire serialized on-chip interconnect using adaptive control schemes.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Packet-switched on-chip interconnection network for system-on-chip applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

Analysis and Implementation of Practical, Cost-Effective Networks on Chips.
IEEE Des. Test Comput., 2005

A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An arbitration look-ahead scheme for reducing end-to-end latency in networks on chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Low energy transmission coding for on-chip serial communications.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

On-chip network based embedded core testing.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

SILENT: serialized low energy transmission coding for on-chip interconnection networks.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

2003
A 10Gbps/port 8×8 shared bus switch with embedded DRAM hierarchical output buffer.
Proceedings of the ESSCIRC 2003, 2003

A high-speed and lightweight on-chip crossbar switch scheduler for on-chip interconnection networks.
Proceedings of the ESSCIRC 2003, 2003

A distributed crossbar switch scheduler for on-chip networks.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002
A 120-mW 3-D rendering engine with 6-Mb embedded DRAM and 3.2-GB/s runtime reconfigurable bus for PDA chip.
IEEE J. Solid State Circuits, 2002

A reconfigurable multilevel parallel texture cache memory with 75-GB/s parallel cache replacement bandwidth.
IEEE J. Solid State Circuits, 2002

Race logic architecture (RALA): a novel logic concept using the race scheme of input variables.
IEEE J. Solid State Circuits, 2002

A practical method to use eDRAM in the shared bus packet switch.
Proceedings of the Global Telecommunications Conference, 2002

2001
An 80/20-MHz 160-mW multimedia processor integrated with embedded DRAM, MPEG-4 accelerator and 3-D rendering engine for mobile applications.
IEEE J. Solid State Circuits, 2001

2000
A 670 ps, 64 bit dynamic low-power adder design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

One chip-low power digital-TCXO with sub-ppm accuracy.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000


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