Scott C. Smith
Orcid: 0000-0001-9863-6637
According to our database1,
Scott C. Smith
authored at least 63 papers
between 2001 and 2023.
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Bibliography
2023
Combining Relaxation With NCL_X for Enhanced Optimization of Asynchronous Null Convention Logic Circuits.
IEEE Access, 2023
2022
Illegal Trojan design and detection in asynchronous NULL Convention Logic and Sleep Convention Logic circuits.
IET Comput. Digit. Tech., 2022
Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism.
J. Electron. Test., 2022
2021
IEEE Trans. Very Large Scale Integr. Syst., 2021
Memristor-Based Variation-Enabled Differentially Private Learning Systems for Edge Computing in IoT.
IEEE Internet Things J., 2021
Proceedings of the IEEE Power & Energy Society Innovative Smart Grid Technologies Conference, 2021
2020
IEEE Trans. Cloud Comput., 2020
J. Real Time Image Process., 2020
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
Implementation of FinFET Based Static NCL Threshold Gates: An Analysis of Design Choice.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Exploiting Dual-Rail Register Invariants for Equivalence Verification of NCL Circuits.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Further Speedup of a Large Word-Width High-Speed Asynchronous Multiply and Accumulate Unit.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
2019
IEEE Trans. Very Large Scale Integr. Syst., 2019
An Equivalence Verification Methodology for Asynchronous Sleep Convention Logic Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
An Equivalence Verification Methodology for Combinational Asynchronous PCHB Circuits.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018
2017
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
An FPGA-based design for joint control and monitoring of permanent magnet synchronous motors.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
2013
Mitigating power- and timing-based side-channel attacks using dual-spacer dual-rail delay-insensitive asynchronous logic.
Microelectron. J., 2013
J. Low Power Electron., 2013
Quantum-dot cellular automaton of asynchronous Null Convention Logic multiplier design.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
2012
Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012
Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012
2010
IEEE Trans. Educ., 2010
Delay-Insensitive Cell Matrix.
Proceedings of the 2010 International Conference on Computer Design, 2010
2009
Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, ISBN: 978-3-031-79800-9, 2009
Proceedings of the 12th International IEEE Conference on Intelligent Transportation Systems, 2009
Particle Swarm Optimization: A Hardware Implementation.
Proceedings of the 2009 International Conference on Computer Design, 2009
Delay-Insensitive Ternary Logic.
Proceedings of the 2009 International Conference on Computer Design, 2009
Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs.
Proceedings of the IEEE International Conference on 3D System Integration, 2009
2008
J. Low Power Electron., 2008
2007
Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2007
IEEE Trans. Very Large Scale Integr. Syst., 2007
Microelectron. J., 2007
Eng. Appl. Artif. Intell., 2007
Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007
2006
J. Syst. Archit., 2006
2005
Development of a large word-width high-speed asynchronous multiply and accumulate unit.
Integr., 2005
Using a VHDL Testbench for Transistor-Level Simulation and Energy Calculation.
Proceedings of the 2005 International Conference on Computer Design, 2005
High-Speed Energy Estimation for Delay-Insensitive Circuits.
Proceedings of the 2005 International Conference on Computer Design, 2005
Implementation of Design For Test for Asynchronous NCL Designs.
Proceedings of the 2005 International Conference on Computer Design, 2005
2004
Design of a NULL Convention Self-Timed Divider.
Proceedings of the International Conference on Embedded Systems and Applications, 2004
Designing NULL Convention Combinational Circuits to Fully Utilize Gate-Level Pipelining for Maximum Throughput.
Proceedings of the International Conference on Embedded Systems and Applications, 2004
2003
IEEE Des. Test Comput., 2003
Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-Wise Completion Strategy.
Proceedings of the International Conference on VLSI, 2003
Design and Characterization of NULL Convention Arithmetic Logic Units.
Proceedings of the International Conference on VLSI, 2003
Proceedings of the American Control Conference, 2003
2002
NULL convention multiply and accumulate unit with conditional rounding, scaling, and saturation.
J. Syst. Archit., 2002
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002
2001