Sayantan Das

Affiliations:
  • Indian Institute of Technology, Kharagpur, India


According to our database1, Sayantan Das authored at least 9 papers between 2004 and 2009.

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Bibliography

2009
Design intent coverage revisited.
ACM Trans. Design Autom. Electr. Syst., 2009

2006
Design-Intent Coverage - A New Paradigm for Formal Property Verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Synthesis of system verilog assertions.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

What lies between design intent coverage and model checking?
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Discovering the input assumptions in specification refinement coverage.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
Formal Methods for Analyzing the Completeness of an Assertion Suite against a High-Level Fault Model.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

SAT based solutions for consistency problems in formal property specifications for open systems.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004
Formal verification coverage: computing the coverage gap between temporal specifications.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Formal Verification Coverage: Are the RTL-Properties Covering the Design's Architectural Intent?
Proceedings of the 2004 Design, 2004


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