Sayandeep Sanyal
Orcid: 0000-0002-6652-9113
According to our database1,
Sayandeep Sanyal
authored at least 13 papers
between 2017 and 2023.
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Bibliography
2023
CoVerPlan: A Comprehensive Verification Planning Framework Leveraging PSS Specifications.
ACM Trans. Design Autom. Electr. Syst., January, 2023
Accelerating Defect Simulation in Analog and Mixed-Signal Circuits by Parallel Defect Injection.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
The CoveRT Approach for Coverage Management in Analog and Mixed-Signal Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022
2021
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Methodology for Biasing Random Simulation for Rapid Coverage of Corner Cases in AMS Designs.
CoRR, 2021
2020
A Methodology for Identification of Internal Nets for Improving Fault Coverage in Analog and Mixed Signal Circuits.
J. Electron. Test., 2020
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020
2019
Fault Classification and Coverage of Analog Circuits using DC Operating Point and Frequency Response Analysis.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
A Structured Approach for Rapid Identification of Fault-Sensitive Nets in Analog Circuits.
Proceedings of the 28th IEEE Asian Test Symposium, 2019
2017
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017