Sayandeep Saha

Orcid: 0000-0002-5535-1102

According to our database1, Sayandeep Saha authored at least 48 papers between 2014 and 2024.

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Bibliography

2024
VALIANT: An EDA Flow for Side-Channel Leakage Evaluation and Tailored Protection.
IEEE Trans. Computers, February, 2024

On the Instability of Softmax Attention-Based Deep Learning Models in Side-Channel Analysis.
IEEE Trans. Inf. Forensics Secur., 2024

Prime Masking vs. Faults - Exponential Security Amplification against Selected Classes of Attacks.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

Carry Your Fault: A Fault Propagation Attack on Side-Channel Protected LWE-based KEM.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024

Harmonizing PUFs for Forward Secure Authenticated Key Exchange with Symmetric Primitives.
IACR Cryptol. ePrint Arch., 2024

Authenticating Edge Neural Network through Hardware Security Modules and Quantum-Safe Key Management.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023
Learn from Your Faults: Leakage Assessment in Fault Attacks Using Deep Learning.
J. Cryptol., July, 2023

Combined Private Circuits - Combined Security Refurbished.
IACR Cryptol. ePrint Arch., 2023

On the Amplification of Cache Occupancy Attacks in Randomized Cache Architectures.
CoRR, 2023

A short note on the paper 'Are Randomized Caches Really Random?'.
CoRR, 2023

TT-TFHE: a Torus Fully Homomorphic Encryption-Friendly Neural Network Architecture.
CoRR, 2023

Are Randomized Caches Truly Random? Formal Analysis of Randomized-Partitioned Caches.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

Non-Profiled Side-Channel Assisted Fault Attack: A Case Study on DOMREP.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

ExploreFault: Identifying Exploitable Fault Models in Block Ciphers with Reinforcement Learning.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Exploring Integrity of AEADs with Faults: Definitions and Constructions.
IACR Trans. Symmetric Cryptol., 2022

Exploring Bitslicing Architectures for Enabling FHE-Assisted Machine Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

<i>NN-Lock</i>: A Lightweight Authorization to Prevent IP Threats of Deep Learning Models.
ACM J. Emerg. Technol. Comput. Syst., 2022

Vulnerability Assessment of Ciphers To Fault Attacks Using Reinforcement Learning.
IACR Cryptol. ePrint Arch., 2022

PUF-COTE: A PUF Construction with Challenge Obfuscation and Throughput Enhancement.
IACR Cryptol. ePrint Arch., 2022

Corruption Exposes You: Statistical Key Recovery from Compound Logic Locking.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

AntiSIFA-CAD: A Framework to Thwart SIFA at the Layout Level.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

TransNet: Shift Invariant Transformer Network for Side Channel Analysis.
Proceedings of the Progress in Cryptology, 2022

2021
TransNet: Shift Invariant Transformer Network for Power Attack.
IACR Cryptol. ePrint Arch., 2021

Shortest Path to Secured Hardware: Domain Oriented Masking with High-Level-Synthesis.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Transform Without Encode is not Sufficient for SIFA and FTA Security: A Case Study.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2021

Divided We Stand, United We Fall: Security Analysis of Some SCA+SIFA Countermeasures Against SCA-Enhanced Fault Template Attacks.
Proceedings of the Advances in Cryptology - ASIACRYPT 2021, 2021

2020
A Framework to Counter Statistical Ineffective Fault Analysis of Block Ciphers Using Domain Transformation and Error Correction.
IEEE Trans. Inf. Forensics Secur., 2020

Fault Attack on SKINNY Cipher.
J. Hardw. Syst. Secur., 2020

Pushing the Limits of Fault Template Attacks: The Role of Side-Channels.
IACR Cryptol. ePrint Arch., 2020

Leakage Assessment in Fault Attacks: A Deep Learning Perspective.
IACR Cryptol. ePrint Arch., 2020

Rowhammer Induced Intermittent Fault Attack on ECC-hardened memory.
IACR Cryptol. ePrint Arch., 2020

Deep-Lock: Secure Authorization for Deep Neural Networks.
CoRR, 2020

Fault Template Attacks on Block Ciphers Exploiting Fault Propagation.
Proceedings of the Advances in Cryptology - EUROCRYPT 2020, 2020

ExplFrame: Exploiting Page Frame Cache for Fault Analysis of Block Ciphers.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

LoPher: SAT-Hardened Logic Embedding on Block Ciphers.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Automatic Characterization of Exploitable Faults: A Machine Learning Approach.
IEEE Trans. Inf. Forensics Secur., 2019

An automated framework for exploitable fault identification in block ciphers.
J. Cryptogr. Eng., 2019

Breach the Gate: Exploiting Observability for Fault Template Attacks on Block Ciphers.
IACR Cryptol. ePrint Arch., 2019

ALAFA: Automatic Leakage Assessment for Fault Attack Countermeasures.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
ExpFault: An Automated Framework for Exploitable Fault Characterization in Block Ciphers.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

Differential Fault Attack on SKINNY Block Cipher.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2018

Breaking Redundancy-Based Countermeasures with Random Faults and Power Side Channel.
Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2018

2017
Differential Fault Analysis Automation.
IACR Cryptol. ePrint Arch., 2017

An Automated Framework for Exploitable Fault Identification in Block Ciphers - A Data Mining Approach.
Proceedings of the PROOFS 2017, 2017

2016
Testability Based Metric for Hardware Trojan Vulnerability Assessment.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015
Improved Test Pattern Generation for Hardware Trojan Detection using Genetic Algorithm and Boolean Satisfiability.
IACR Cryptol. ePrint Arch., 2015

2014
Composite PUF: A new design paradigm for Physically Unclonable Functions on FPGA.
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014

Fault attack on AES via hardware Trojan insertion by dynamic partial reconfiguration of FPGA over ethernet.
Proceedings of the 9th Workshop on Embedded Systems Security, 2014


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