Sayan Tripathi

According to our database, Sayan Tripathi authored at least 9 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

FPGA implementation of compact and low-power multiplierless architectures for DWT and IDWT.

Jhilam Jana, Ritesh Sur Chowdhury, Sayan Tripathi, Jaydeb Bhaumik

J. Real Time Image Process., February, 2024

Improved DWT and IDWT architectures for image compression.

Ritesh Sur Chowdhury, Jhilam Jana, Sayan Tripathi, Jaydeb Bhaumik

Microprocess. Microsystems, 2024

2023

New low power and fast SEC-DAEC and SEC-DAEC-TAEC codes for memories in space application.

Sayan Tripathi, Jhilam Jana, Jaydeb Bhaumik

Integr., March, 2023

Implementation of Fast and Power Efficient SEC-DAEC and SEC-DAEC-TAEC Codecs on FPGA.

Sayan Tripathi, Jhilam Jana, Jaydeb Bhaumik

CoRR, 2023

2020

Lower complexity error location detection block of adjacent error correcting decoder for SRAMs.

Raj Kumar Maity, Sayan Tripathi, Jagannath Samanta, Jaydeb Bhaumik

IET Comput. Digit. Tech., 2020

Design of SEC-DED and SEC-DED-DAEC Codes of different lengths.

Sayan Tripathi, Jhilam Jana, Jaydeb Bhaumik

CoRR, 2020

2019

Comments on "a novel approach of error detection and correction for efficient energy in wireless networks".

Jagannath Samanta, Sayan Tripathi

Multim. Tools Appl., 2019

Fast and Power Efficient SEC-DED and SEC-DED-DAEC Codes in IoT based Wireless Sensor Networks.

Sayan Tripathi, Jhilam Jana, Jagannath Samanta, Jaydeb Bhaumik

Proceedings of the TENCON 2019, 2019

Design and Development of Electronics Pest Repellent Using PIR Sensor and 8051 Micro-Controller.

Jhilam Jana, Sayan Tripathi, Asim Kumar Jana, Malay Kumar Pandit

Proceedings of the Recent Advances in Intelligent Information Systems and Applied Mathematics, 2019