Sayak Ray

According to our database1, Sayak Ray authored at least 23 papers between 2007 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Optimal Placement of TDC Sensor for Enhanced Power Side-Channel Assessment on FPGAS.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023
An Exhaustive Approach to Detecting Transient Execution Side Channels in RTL Designs of Processors.
IEEE Trans. Computers, 2023

Secure-by-Construction Design Methodology for CPUs: Implementing Secure Speculation on the RTL.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Power Side-Channel Vulnerability Assessment of Lightweight Cryptographic Scheme, XOODYAK.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Automating hardware security property generation: invited.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2019
Verification of Authenticated Firmware Load.
IACR Cryptol. ePrint Arch., 2019

Verification of Authenticated Firmware Loaders.
Proceedings of the 2019 Formal Methods in Computer Aided Design, 2019

Formal Verification of Security Critical Hardware-Firmware Interactions in Commercial SoCs.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardware.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Malware detection using machine learning based analysis of virtual memory access patterns.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2015
Evaluating the security of logic encryption algorithms.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2015

Template-based Synthesis of Instruction-Level Abstractions for SoC Verification.
Proceedings of the Formal Methods in Computer-Aided Design, 2015

BEE: Predicting realistic worst case and stochastic eye diagrams by accounting for correlated bitstreams and coding strategies.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Effective abstraction for response proof of communication fabrics.
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014

NINJA: boolean modelling and formal verification of tiered-rate chemical reaction networks (extended abstract).
Proceedings of the 5th ACM Conference on Bioinformatics, 2014

ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Scalable Model Checking Beyond Safety - A Communication Fabric Perspective.
PhD thesis, 2013

Ranking structure in communication fabrics.
Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013

2012
A dynamic assertion-based verification platform for validation of UML designs.
ACM SIGSOFT Softw. Eng. Notes, 2012

Mapping into LUT structures.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Scalable progress verification in credit-based flow-control systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Enhancing ABC for stabilization verification of SystemVerilog/VHDL models.
Proceedings of the First International Workshop on Design and Implementation of Formal Tools and Systems, 2011

2007
A New Pseudo-Boolean Satisfiability based approach to Power Mode Schedulability Analysis.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007


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