Savvas G. Chamberlain

According to our database, Savvas G. Chamberlain authored at least 8 papers between 1980 and 1995.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1995

An Architecture for Integrated Reliability Simulators Using Analog Hardware Description Languages.

S. M. GadelRab, James A. Barby, Savvas G. Chamberlain

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1992

A numerical model for two-dimensional transient simulation of amorphous silicon thin-film transistors.

John R. F. McMacken, Savvas G. Chamberlain

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

1991

Buried-channel MOSFET model for SPICE.

Michael J. Van der Tol, Savvas G. Chamberlain

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

1989

A CMOS model for computer-aided circuit analysis and design.

James W. Roberts, Savvas G. Chamberlain

IEEE J. Solid State Circuits, February, 1989

A compact thermal noise model for the investigation of soft error rates in MOS VLSI digital circuits.

Paul Layman, Savvas G. Chamberlain

IEEE J. Solid State Circuits, February, 1989

CHORD: a modular semiconductor device simulation development tool incorporating external network models.

John R. F. McMacken, Savvas G. Chamberlain

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

1984

Foreword.

Constantine N. Anagnostopoulos, Savvas G. Chamberlain

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

1980

Design and Realization of a Two-Level 64K Byte CCD Memory System for Microcomputer Applications.

Robert J. Inkol, Savvas G. Chamberlain

IEEE Trans. Computers, 1980