Saurabh Kotiyal

Orcid: 0009-0005-2143-2763

According to our database1, Saurabh Kotiyal authored at least 11 papers between 2005 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2016
Design Methodologies for Reversible Logic Based Barrel Shifters.
J. Circuits Syst. Comput., 2016

2015
Reversible logic based multiplication computing unit using binary tree data structure.
J. Supercomput., 2015

2014
Reversible Logic Based Design and Test of Field Coupled Nanocomputing Circuits.
Proceedings of the Field-Coupled Nanocomputing - Paradigms, Progress, and Perspectives, 2014

Design of Reversible Adder-Subtractor and its Mapping in Optical Computing Domain.
Trans. Comput. Sci., 2014

Efficient reversible NOR gates and their mapping in optical computing domain.
Microelectron. J., 2014

Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage Bits.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2013
Design of Testable Reversible Sequential Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2013

2012
Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Mach-Zehnder interferometer based design of all optical reversible binary adder.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2006
Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2005
VLSI Implementation of O(n*n) Sorting Algorithms And Their Hardware Comparison.
Proceedings of The 2005 International Conference on Scientific Computing, 2005


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