Saumya Bhadauria
Orcid: 0000-0002-6502-2695
According to our database1,
Saumya Bhadauria
authored at least 26 papers
between 2014 and 2024.
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Bibliography
2024
SCL: A sustainable deep learning solution for edge computing ecosystem in smart manufacturing.
J. Ind. Inf. Integr., 2024
2023
J. Ind. Inf. Integr., August, 2023
2022
A cost aware topology formation scheme for latency sensitive applications in edge infrastructure-as-a-service paradigm.
J. Netw. Comput. Appl., 2022
Watermarking of Deep Recurrent Neural Network Using Adversarial Examples to Protect Intellectual Property.
Appl. Artif. Intell., 2022
Proceedings of the IEEE 15th International Conference on Cloud Computing, 2022
2021
Hybrid Intrusion Detection System using an Unsupervised method for Anomaly-based Detection.
Proceedings of the IEEE International Conference on Advanced Networks and Telecommunications Systems, 2021
Proceedings of the IEEE International Conference on Advanced Networks and Telecommunications Systems, 2021
2020
Proceedings of the 14th IEEE International Conference on Advanced Networks and Telecommunications Systems, 2020
2019
Proceedings of the 2019 International Carnahan Conference on Security Technology, 2019
Demand prediction for e-commerce advertisements: A comparative study using state-of-the-art machine learning methods.
Proceedings of the 10th International Conference on Computing, 2019
2018
Proceedings of the IEEE International Conference on Advanced Networks and Telecommunications Systems, 2018
2017
TL-HLS: Methodology for Low Cost Hardware Trojan Security Aware Scheduling With Optimal Loop Unrolling Factor During High Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
Low cost optimized Trojan secured schedule at behavioral level for single & Nested loop control data flow graphs (Invited Paper).
Integr., 2017
2016
Exploring Low Cost Optimal Watermark for Reusable IP Cores During High Level Synthesis.
IEEE Access, 2016
Embedding low cost optimal watermark during high level synthesis for reusable IP core protection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
2015
Bacterial foraging driven exploration of multi cycle fault tolerant datapath based on power-performance tradeoff in high level synthesis.
Expert Syst. Appl., 2015
Adaptive bacterial foraging driven datapath optimization: Exploring power-performance tradeoff in high level synthesis.
Appl. Math. Comput., 2015
Automated design space exploration of multi-cycle transient fault detectable datapath based on multi-objective user constraints for application specific computing.
Adv. Eng. Softw., 2015
Automated design space exploration of transient fault detectable datapath based on user specified power and delay constraints.
Proceedings of the VLSI Design, Automation and Test, 2015
User power-delay budget driven PSO based design space exploration of optimal k-cycle transient fault secured datapath during high level synthesis.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015
Secure Information Processing during System-Level: Exploration of an Optimized Trojan Secured Datapath for CDFGs during HLS Based on User Constraints.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015
Untrusted Third Party Digital IP Cores: Power-Delay Trade-off Driven Exploration of Hardware Trojan Secured Datapath during High Level Synthesis.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
2014
Exploration of Multi-objective Tradeoff during High Level Synthesis Using Bacterial Chemotaxis and Dispersal.
Proceedings of the 18th International Conference in Knowledge Based and Intelligent Information and Engineering Systems, 2014
Error Masking of Transient Faults: Exploration of a Fault Tolerant Datapath Based on User Specified Power and Delay Budget.
Proceedings of the 2014 International Conference on Information Technology, 2014
Automated exploration of datapath in high level synthesis using temperature dependent bacterial foraging optimization algorithm.
Proceedings of the IEEE 27th Canadian Conference on Electrical and Computer Engineering, 2014