Saumil Shah

Orcid: 0000-0003-1642-4687

According to our database1, Saumil Shah authored at least 16 papers between 2004 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Translational oncology: bringing theory and clinic one step closer: Blackboard to bench, and back
PhD thesis, 2023

Uncertainty Estimation for a Dual-Embedding based Entity Extraction Service.
Proceedings of the IEEE International Conference on Big Data, 2023

2021
The impact of phenotypic heterogeneity of tumour cells on treatment and relapse dynamics.
PLoS Comput. Biol., 2021

2018
Real-time face recognition in HD videos: Algorithms and framework.
Proceedings of the 2018 Annual IEEE International Systems Conference, 2018

Automated human capital management system.
Proceedings of the 2018 Annual IEEE International Systems Conference, 2018

2017
Attitude Control of the Asteroid Origins Satellite 1 (AOSAT 1).
CoRR, 2017

2009
Efficient smart sampling based full-chip leakage analysis for intra-die variation considering state dependence.
Proceedings of the 46th Design Automation Conference, 2009

2008
A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Variability in nanometer CMOS: Impact, analysis, and minimization.
Integr., 2008

Investigation of diffusion rounding for post-lithography analysis.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Line-End Shortening is Not Always a Failure.
Proceedings of the 44th Design Automation Conference, 2007

2006
Standard cell library optimization for leakage reduction.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Discrete Vt assignment and gate sizing using a self-snapping continuous formulation.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance.
Proceedings of the 42nd Design Automation Conference, 2005

2004
A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004


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