Satyamurthy Pullela

According to our database, Satyamurthy Pullela authored at least 10 papers between 1993 and 1998.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

1998

CMOS Combinational Circuit Sizing by Stage-wise Tapering.

Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija

Proceedings of the 1998 Design, 1998

1997

Clock Distribution Methodology for PowerPC^TM Microprocessors.

Shantanu Ganguly, Daksh Lehther, Satyamurthy Pullela

J. VLSI Signal Process., 1997

Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets.

Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor.

Abhijit Dharchoudhury, David T. Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Library-less synthesis for static CMOS combinational logic circuits.

Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996

Post-processing of clock trees via wiresizing and buffering for robust design.

Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1995

Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization.

Noel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi

Proceedings of the 32st Conference on Design Automation, 1995

1994

Modeling the "Effective capacitance" for the RC interconnect of CMOS gates.

Jessica Qian, Satyamurthy Pullela, Lawrence T. Pillage

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

RC interconnect synthesis-a moment fitting approach.

Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993

Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization.

Satyamurthy Pullela, Noel Menezes, Lawrence T. Pillage

Proceedings of the 30th Design Automation Conference. Dallas, 1993