Satyabrata Sarangi

Orcid: 0000-0003-2988-3698

According to our database1, Satyabrata Sarangi authored at least 6 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Energy-efficient canonical Huffman decoders on many-core processor arrays and FPGAs.
Integr., 2023

2022
Hardware Architectures for Lossless Compression
PhD thesis, 2022

2021
DeepScaleTool: A Tool for the Accurate Estimation of Technology Scaling in the Deep-Submicron Era.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Canonical Huffman Decoder on Fine-grain Many-core Processor Arrays.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2015
Efficient Hardware Implementation of Encoder and Decoder for Golay Code.
IEEE Trans. Very Large Scale Integr. Syst., 2015

2014
Comparative Analysis of Golay Code Based Excitation and Coherent Averaging for Non-invasive Glucose Monitoring System.
Proceedings of the 2014 IEEE 27th International Symposium on Computer-Based Medical Systems, 2014


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