Satya K. Vendra

According to our database, Satya K. Vendra authored at least 3 papers between 2018 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2021

Fast Buffer Count Estimation in 3D IC Floorplanning.

Sucheta Mohapatra, Satya K. Vendra, Malgorzata Chrzanowska-Jeske

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Fast Thermal Goodness Evaluation of a 3D-IC Floorplan.

Satya K. Vendra, Malgorzata Chrzanowska-Jeske

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

2018

Buffered-Interconnect Performance and Power Dissipation in 3D ICs with Temperature Profile.

Satya K. Vendra, Malgorzata Chrzanowska-Jeske

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018