Satoshi Uemori

According to our database1, Satoshi Uemori authored at least 8 papers between 2010 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2013
Multi-bit Sigma-Delta TDC Architecture with Improved Linearity.
J. Electron. Test., 2013

2012
Multi-bit sigma-delta TDC architecture with self-calibration.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
Background Self-Calibration Algorithm for Pipelined ADC Using Split ADC Scheme.
IEICE Trans. Electron., 2011

Design for Testability That Reduces Linearity Testing Time of SAR ADCs.
IEICE Trans. Electron., 2011

2010
Background calibration algorithm for pipelined ADC with open-loop residue amplifier using split ADC structure.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

ADC linearity test signal generation algorithm.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

SAR ADC that is configurable to optimize yield.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Stochastic TDC architecture with self-calibration.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010


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