Satoshi Tayu

Proceedings of the Computing and Combinatorics - 23rd International Conference, 2017

2016

On the Three-Dimensional Channel Routing.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

On orthogonal ray trees.

[BibT_eX]

[DOI]

Discret. Appl. Math., 2016

2015

Dominating Sets in Two-Directional Orthogonal Ray Graphs.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2015

OBDD Representation of Intersection Graphs.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2015

A Note on Harmonious Coloring of Caterpillars.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2015

On Evasion Games on Graphs.

[BibT_eX]

[DOI]

Proceedings of the Discrete and Computational Geometry and Graphs - 18th Japan Conference, 2015

2014

Dominating Sets and Induced Matchings in Orthogonal Ray Graphs.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2014

Weighted dominating sets and induced matchings in orthogonal ray graphs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Control, 2014

A note on the energy-aware mapping for NoCs.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

On Minimum Feedback Vertex Sets in Bipartite Graphs and Degree-Constraint Graphs.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2013

2012

Bandwidth of convex bipartite graphs and related graphs.

[BibT_eX]

[DOI]

Inf. Process. Lett., 2012

On Minimum Feedback Vertex Sets in Graphs.

[BibT_eX]

[DOI]

Proceedings of the Third International Conference on Networking and Computing, 2012

2011

On Two Problems of Nano-PLA Design.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2011

2010

On orthogonal ray graphs.

[BibT_eX]

[DOI]

Discret. Appl. Math., 2010

On two-directional orthogonal ray graphs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Universal Test Sets for Reversible Circuits.

[BibT_eX]

[DOI]

Shota Fukuyama

Proceedings of the Computing and Combinatorics, 16th Annual International Conference, 2010

2009

On the two-dimensional orthogonal drawing of series-parallel graphs.

[BibT_eX]

[DOI]

Kumiko Nomura

Discret. Appl. Math., 2009

On the Three-dimensional Orthogonal Drawing of Outerplanar Graphs.

[BibT_eX]

[DOI]

Takuya Oshima

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Orthogonal Ray Graphs and Nano-PLA Design.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

Cost-Constrained Minimum-Delay Multicasting.

[BibT_eX]

[DOI]

Turki Ghazi Al-Mutairi

J. Interconnect. Networks, 2008

On Fault Testing for Reversible Circuits.

[BibT_eX]

[DOI]

Shigeru Ito

IEICE Trans. Inf. Syst., 2008

On the three-dimensional orthogonal drawing of series-parallel graphs (extended abstract).

[BibT_eX]

[DOI]

Kumiko Nomura

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007

On the Complexity of Three-Dimensional Channel Routing (Extended Abstract).

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2005

On the Orthogonal Drawing of Outerplanar Graphs.

[BibT_eX]

[DOI]

Kumiko Nomura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

On the three-dimensional channel routing.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003

A simulated annealing approach with sequence-pair encoding using a penalty function for the placement problem with boundary constraints.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Characterization and Computation of Steiner Routing Based on Elmore's Delay Model.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

Scheduling Trees onto Hypercubes and Grids.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2002

3D scheduling based on code space exploration for dynamically reconfigurable systems.

[BibT_eX]

[DOI]

Jun'ichi Yokoyama

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Characterization and computation of Steiner wiring based on Elmore's delay model.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2000

An Approximation Algorithm for Multiprocessor Scheduling of Trees with Communication Delays.

[BibT_eX]

[DOI]

Motoyasu Katsura

Proceedings of the 5th International Symposium on Parallel Architectures, 2000

Exact and heuristic methods of assignment driven scheduling for data-path synthesis applications.

[BibT_eX]

[DOI]

Yoshitaka Nishio

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Assignment-Space Exploration Approach to Concurrent Data-Path/Floorplan Synthesis.

[BibT_eX]

[DOI]

Koji Ohashi

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1999

Scheduling Trees onto Hypercubes and Grids Is NP-complete.

[BibT_eX]

[DOI]