Satoshi Shigematsu

According to our database, Satoshi Shigematsu authored at least 35 papers between 1995 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

Hierarchical Scheduling with FPGA-based Accelerator for Flexible 5G Mobile Networks.

Yuki Arikawa, Takeshi Sakamoto, Satoshi Shigematsu

Proceedings of the 91st IEEE Vehicular Technology Conference, 2020

Miniature Optical Connector with Magnetic Physical Contact.

Kota Shikama, Norio Sato, Atsushi Aratake, Satoshi Shigematsu, Takeshi Sakamoto

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020

2019

Proximity Gettering Design of Hydrocarbon-Molecular-Ion-Implanted Silicon Wafers Using Dark Current Spectroscopy for CMOS Image Sensors.

Kazunari Kurita, Takeshi Kadono, Satoshi Shigematsu, Ryo Hirose, Ryosuke Okuyama, Ayumi Onaka-Masada, Hidehiko Okuda, Yoshihiro Koga

Sensors, 2019

5G R&D Activities for High Capacity Technologies with Ultra High-Density Multi-Band and Multi-Access Layered Cells.

Morihiko Minowa, Hiroyuki Seki, Yukihiko Okumura, Satoshi Suyama, Jun Terada, Satoshi Shigematsu, Yasushi Takatori, Hiroaki Asano, Yukio Hirano, Yasushi Yamao, Fumiyuki Adachi, Masataka Nakazawa

Proceedings of the 89th IEEE Vehicular Technology Conference, 2019

2018

Throughput Enhancement with Hardware Accelerated Resource Scheduler in Low-Latency 5G Systems.

Yuki Arikawa, Takeshi Sakamoto, Shunji Kimura, Satoshi Shigematsu

Proceedings of the 29th IEEE Annual International Symposium on Personal, 2018

Contention-Less Scheduling-Free Torus Optical Network Comprising Thousands of Nodes.

Salah Ibrahim, Toshikazu Hashimoto, Satoshi Shigematsu

Proceedings of the European Conference on Optical Communication, 2018

2017

A 100-MHz 51.2-Gb/s Packet Lookup Engine with Automatic Table Update Function.

Kousuke Imamura, Ryota Honda, Yoshifumi Kawamura, Naoki Miura, Masami Urano, Satoshi Shigematsu, Tetsuya Matsumura, Yoshio Matsuda

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

2016

High-speed radio-resource scheduling for 5G ultra-high-density distributed antenna systems.

Yuki Arikawa, Hiroyuki Uzawa, Takeshi Sakamoto, Satoshi Shigematsu

Proceedings of the 8th International Conference on Wireless Communications & Signal Processing, 2016

2015

Software-Hardware-Cooperative Protocol Processor for Extendable 10G-EPON MAC Chip.

Naoki Miura, Akihiko Miyazaki, Junichi Kato, Nobuyuki Tanaka, Satoshi Shigematsu, Masami Urano, Mamoru Nakanishi, Tsugumichi Shibata

IEICE Trans. Electron., 2015

A 100-MHz 51.2-Gb/s packet lookup engine LSI based on missmatch detection circuit combined with linked-list hash table.

Yoshifumi Kawamura, Kousuke Imamura, Naoki Miura, Masami Urano, Satoshi Shigematsu, Yoshio Matsuda

Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015

Practical resource scheduling in massive-cell deployment for 5G mobile communications systems.

Yuki Arikawa, Kenji Kawai, Hiroyuki Uzawa, Satoshi Shigematsu

Proceedings of the 2015 International Symposium on Intelligent Signal Processing and Communication Systems, 2015

Data transmission scheme for enhancing effective downlink bandwidth in 5G mobile fronthaul with TDM-PON.

Hiroyuki Uzawa, Yuki Arikawa, Kenji Kawai, Satoshi Shigematsu

Proceedings of the European Conference on Optical Communication, 2015

High-speed sorted-table search scheme for network processing.

Hiroyuki Uzawa, Kazuhiko Terada, Namiko Ikeda, Satoshi Shigematsu

Proceedings of the 21st Asia-Pacific Conference on Communications, 2015

2014

Area-efficient dynamically reconfigurable protocol-processing-hardware for access network communications SoC.

Saki Hatta, Nobuyuki Tanaka, Satoshi Shigematsu

Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

A novel DBA scheme for TDM-PON based mobile fronthaul.

Takayoshi Tashiro, Shigeru Kuwano, Jun Terada, Tomoaki Kawamura, Nobuyuki Tanaka, Satoshi Shigematsu, Naoto Yoshimoto

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2014

2012

Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference.

Alice Wang, Ken Takeuchi, Tanay Karnik, Maysam Ghovanloo, Satoshi Shigematsu

IEEE J. Solid State Circuits, 2012

Wire-speed verification schemes for HW/SW design of 10-Gbit/s-class large-scale NW SoC using multiple FPGAs.

Kazuhiko Terada, Hiroyuki Uzawa, Namiko Ikeda, Satoshi Shigematsu, Nobuyuki Tanaka, Masami Urano

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2010

Capacitive-Sensing Circuit Technique for Image Quality Improvement on Fingerprint Sensor LSIs.

Toshishige Shimamura, Hiroki Morimura, Satoshi Shigematsu, Mamoru Nakanishi, Katsuyuki Machida

IEEE J. Solid State Circuits, 2010

Fusion of MEMS and circuits.

Satoshi Shigematsu, Kazutami Arimoto, Christoph Hagleitner

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2008

A Fingerprint Sensor with Impedance Sensing for Fraud Detection.

Toshishige Shimamura, Hiroki Morimura, Nobuhiro Shimoyama, Tomomi Sakata, Satoshi Shigematsu, Katsuyuki Machida, Mamoru Nakanishi

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI.

Satoshi Shigematsu, Hiroki Morimura, Toshishige Shimamura, Takahiro Hatano, Namiko Ikeda, Yukio Okazaki, Katsuyuki Machida, Mamoru Nakanishi

IEICE Trans. Electron., 2007

2006

Fingerprint Image Enhancement and Rotation Schemes for a Single-Chip Fingerprint Sensor and Identifier.

Satoshi Shigematsu, Koji Fujii, Hiroki Morimura, Takahiro Hatano, Mamoru Nakanishi, Namiko Ikeda, Toshishige Shimamura, Katsuyuki Machida, Yukio Okazaki, Hakaru Kyuragi

IEICE Trans. Electron., 2006

2005

Pixel-Parallel Image-Matching Circuit Schemes for a Single-Chip Fingerprint Sensor and Identifier.

Satoshi Shigematsu, Hiroki Morimura, Katsuyuki Machida, Yukio Okazaki, Hakaru Kyuragi

IEICE Trans. Electron., 2005

2002

A pixel-level automatic calibration circuit scheme for capacitive fingerprint sensor LSIs.

Hiroki Morimura, Satoshi Shigematsu, Toshishige Shimamura, Katsuyuki Machida, Hakaru Kyuragi

IEEE J. Solid State Circuits, 2002

Fingerprint Image Enhancement by Pixel-Parallel Processing.

Namiko Ikeda, Mamoru Nakanishi, Koji Fujii, Takahiro Hatano, Satoshi Shigematsu, Takuya Adachi, Yukio Okazaki, Hakaru Kyuragi

Proceedings of the 16th International Conference on Pattern Recognition, 2002

A Fingerprint Verification Algorithm Using the Differential Matching Rate.

Takahiro Hatano, Takuya Adachi, Satoshi Shigematsu, Hiroki Morimura, Shigehiko Onishi, Yukio Okazaki, Hakaru Kyuragi

Proceedings of the 16th International Conference on Pattern Recognition, 2002

A 500-dpi cellular-logic processing array for fingerprint-image enhancement and verification.

Koji Fujii, Mamoru Nakanishi, Satoshi Shigematsu, Hiroki Morimura, Takahiro Hatano, Namiko Ikeda, Toshishige Shimamura, Yukio Okazaki, Hakaru Kyuragi

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2000

A novel sensor cell architecture and sensing circuit scheme for capacitive fingerprint sensors.

Hiroki Morimura, Satoshi Shigematsu, Katsuyuki Machida

IEEE J. Solid State Circuits, 2000

1999

A single-chip fingerprint sensor and identifier.

Satoshi Shigematsu, Hiroki Morimura, Yasuyuki Tanabe, Takuya Adachi, Katsuyuki Machida

IEEE J. Solid State Circuits, 1999

A shared-bitline SRAM cell architecture for 1-V ultra low-power word-bit configurable macrocells.

Hiroki Morimura, Satoshi Shigematsu, Shinsuke Konaka

Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs.

Shinichiro Mutoh, Satoshi Shigematsu, Yoshinori Gotoh, Shinsuke Konaka

Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1997

A 1-V high-speed MTCMOS circuit scheme for power-down application circuits.

Satoshi Shigematsu, Shin'ichiro Mutoh, Yasuyuki Matsuya, Yasuyuki Tanabe, Junzo Yamada

IEEE J. Solid State Circuits, 1997

A 0.5-V MTCMOS/SIMOX logic gate.

Takakuni Douseki, Satoshi Shigematsu, Junzo Yamada, Mitsuru Harada, Hiroshi Inokawa, Toshiaki Tsuchiya

IEEE J. Solid State Circuits, 1997

1996

A 1-V multithreshold-voltage CMOS digital signal processor for mobile phone application.

Shinichiro Mutoh, Satoshi Shigematsu, Yasuyuki Matsuya, H. Fukuda, T. Kaneko, Junzo Yamada

IEEE J. Solid State Circuits, 1996

1995

1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS.

Shin'ichiro Mutoh, Takakuni Douseki, Yasuyuki Matsuya, Takahko Aoki, Satoshi Shigematsu, Junzo Yamada

IEEE J. Solid State Circuits, August, 1995