Satoshi Ohtake

According to our database, Satoshi Ohtake authored at least 59 papers between 1997 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Field Monitoring System for Frost Damage Warning and Quality Difference Analysis of Tea Leaves.

Shunsuke Mukai, Satoshi Ohtake

Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023

Hardware Implementation of Constant Monitoring System of Fetal Heart Sounds.

Funakoshi Miyabi, Satoshi Ohtake

Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023

A Method of Controlling Devices Remotely in Online Embedded System Engineer Training.

Toshiyuki Haramaki, Satoshi Ohtake

Proceedings of the International Conference on Consumer Electronics - Taiwan, 2023

Vibration Measurement Experiment of Rails at Shinkansen Rail Yard in Kumamoto.

Shunsuke Mukai, Satoshi Ohtake

Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023

2022

A robust method of IC seating inspection in burn-in sockets using Hough transform.

Tsuneo Kagawa, Masaya Ikemoto, Satoshi Ohtake

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2022

2021

Vibration Measurement of Signal Bonds for Shinkansen.

Yuki Echigo, Satoshi Ohtake

Proceedings of the IEEE International Conference on Consumer Electronics, 2021

2020

Temperature Monitoring in Shinkansen Signal and Communication House.

Yui Uehara, Satoshi Ohtake

Proceedings of the 2020 IEEE International Conference on Consumer Electronics (ICCE), 2020

A Warning System with Multiple Sensors for Avoiding Collision of Bicycles.

Kotaro Iwamoto, Satoshi Ohtake

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020

2019

Factory Environment Monitoring: A Japanese Tea Manufacturer's Case.

Yui Uehara, Satoshi Ohtake

Proceedings of the IEEE International Conference on Consumer Electronics, 2019

A Koji Temperature Monitoring System.

Yui Uehara, Satoshi Ohtake, Takayuki Karyu

Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2019

Monitoring Sake Brewing Processes with Compact Wireless Sensors.

Yui Uehara, Satoshi Ohtake, Takamoto Fukura

Proceedings of the 9th IEEE International Conference on Consumer Electronics, 2019

A Built-In Self-Diagnostic Mechanism for Delay Faults Based on Self-Generation of Expected Signatures.

Yushiro Hiramoto, Satoshi Ohtake, Hiroshi Takahashi

Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018

A Method of Hardware-Trojan Detection Using Design Verification Techniques.

Yushiro Hiramoto, Satoshi Ohtake

Proceedings of the Complex, Intelligent, and Software Intensive Systems, 2018

2017

An approach to LFSR-based X-masking for built-in self-test.

Satoshi Ohtake, Daichi Shimazu

Proceedings of the 18th IEEE Latin American Test Symposium, 2017

2015

A Method of Diagnostic Test Generation for Transition Faults.

Renji Ono, Satoshi Ohtake

Proceedings of the 21st IEEE Pacific Rim International Symposium on Dependable Computing, 2015

A method of one-pass seed generation for LFSR-based deterministic/pseudo-random testing of static faults.

Takanori Moriyasu, Satoshi Ohtake

Proceedings of the 16th Latin-American Test Symposium, 2015

A method of LFSR seed generation for hierarchical BIST.

Kosuke Sawaki, Satoshi Ohtake

Proceedings of the 10th International Design & Test Symposium, 2015

A Delay Measurement Mechanism for Asynchronous Circuits of Bundled-Data Model.

Shuichi Sato, Satoshi Ohtake

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2013

A Method of LFSR Seed Generation for Scan-Based BIST Using Constrained ATPG.

Takanori Moriyasu, Satoshi Ohtake

Proceedings of the Seventh International Conference on Complex, 2013

2011

Delay Testing: Improving Test Quality and Avoiding Over-testing.

Seiji Kajihara, Satoshi Ohtake, Tomokazu Yoneda

IPSJ Trans. Syst. LSI Des. Methodol., 2011

F-Scan: A DFT Method for Functional Scan at RTL.

Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2011

F-Scan Test Generation Model for Delay Fault Testing at RTL Using Standard Full Scan ATPG.

Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the 16th European Test Symposium, 2011

2010

A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification.

Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2010

Constrained ATPG for functional RTL circuits using F-Scan.

Marie Engelene J. Obien, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the 2011 IEEE International Test Conference, 2010

Enabling False Path Identification from RTL for Reducing Design and Test Futileness.

Hiroshi Iwata, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

A synthesis method to propagate false path information from RTL to gate level.

Satoshi Ohtake, Hiroshi Iwata, Hideo Fujiwara

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits.

Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

A Synthesis Method to Alleviate Over-Testing of Delay Faults Based on RTL Don't Care Path Identification.

Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara

Proceedings of the 27th IEEE VLSI Test Symposium, 2009

Fast false path identification based on functional unsensitizability using RTL information.

Yuki Yoshikawa, Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008

Design for Testability Method to Avoid Error Masking of Software-Based Self-Test for Processors.

Masato Nakasato, Michiko Inoue, Satoshi Ohtake, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2008

Identifying Non-Robust Untestable RTL Paths in Circuits with Multi-cycle Paths.

Thomas Edison Yu, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability.

Masato Nakasato, Satoshi Ohtake, Kewal K. Saluja, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2007

Efficient path delay test generation based on stuck-at test generation using checker circuitry.

Tsuyoshi Iwagaki, Satoshi Ohtake, Mineo Kaneko, Hideo Fujiwara

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

False Path Identification using RTL Information and Its Application to Over-testing Reduction for Delay Faults.

Yuki Yoshikawa, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the 16th Asian Test Symposium, 2007

2006

Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation.

Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

A New Test Generation Model for Broadside Transition Testing of Partial Scan Circuits.

Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the IFIP VLSI-SoC 2006, 2006

Low-Cost Hardening of Image Processing Applications Against Soft Errors.

Ilia Polian, Bernd Becker, Masato Nakasato, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Electrical Behavior of GOS Fault affected Domino Logic Cell.

Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

Design for Testability of Software-Based Self-Test for Processors.

Masato Nakazato, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara

Proceedings of the 15th Asian Test Symposium, 2006

2005

Acceleration of transition test generation for acyclic sequential circuits utilizing constrained combinational stuck-at test generation.

Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the 10th European Test Symposium, 2005

Design for Testability Based on Single-Port-Change Delay Testing for Data Paths.

Yuki Yoshikawa, Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

A DFT Method for RTL Data Paths Based on Partially Strong Testability to Guarantee Complete Fault Efficiency.

Hiroyuki Iwata, Tomokazu Yoneda, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

New Non-Scan DFT Techniques to Achieve 100% Fault Efficiency.

Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara

J. Electron. Test., 2004

A design methodology to realize delay testable controllers using state transition information.

Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the 9th European Test Symposium, 2004

2003

A Method of Test Generation fo Path Delay Faults Using Stuck-at Fault Test Generation Algorithms.

Satoshi Ohtake, Kouhei Ohtani, Hideo Fujiwara

Proceedings of the 2003 Design, 2003

Reducibility of Sequential Test Generation to Combinational Test Generation for Several Delay Fault Models.

Tsuyoshi Iwagaki, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

A nonscan DFT method for controllers to provide complete fault efficiency.

Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara

Syst. Comput. Jpn., 2002

A Method of Test Generation for Path Delay Faults in Balanced Sequential Circuits.

Satoshi Ohtake, Hideo Fujiwara, Shunjiro Miwa

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Design for Two-Pattern Testability of Controller-Data Path Circuits.

Atlaf Ul Amin, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Testable Design of Sequential Circuits with Improved Fault Efficiency.

Debesh Kumar Das, Bhargab B. Bhattacharya, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Design for Hierarchical Two-Pattern Testability of Data Paths.

Md. Altaf-Ul-Amin, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability.

Satoshi Ohtake, Shintaro Nagai, Hiroki Wada, Hideo Fujiwara

Proceedings of ASP-DAC 2001, 2001

2000

A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency.

Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara

J. Electron. Test., 2000

A non-scan DFT method at register-transfer level to achieve complete fault efficiency.

Satoshi Ohtake, Hiroki Wada, Toshimitsu Masuzawa, Hideo Fujiwara

Proceedings of ASP-DAC 2000, 2000

1999

A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description.

Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency.

Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

A Non-Scan DFT Method for Controllers to Achieve Complete Fault Efficiency.

Satoshi Ohtake, Toshimitsu Masuzawa, Hideo Fujiwara

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

A sequential circuit structure with combinational test generation complexity and its application.

Hideo Fujiwara, Satoshi Ohtake, Tomoya Takasaki

Syst. Comput. Jpn., 1997

Sequential Test Generation Based on Circuit Pseudo-Transformation.

Satoshi Ohtake, Tomoo Inoue, Hideo Fujiwara

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997