Satoshi Nakano
Orcid: 0000-0002-5114-3242
According to our database1,
Satoshi Nakano
authored at least 16 papers
between 2004 and 2023.
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Bibliography
2023
Customer demand concentration in online grocery retailing: Differences between online and physical store shopping baskets.
Electron. Commer. Res. Appl., November, 2023
Autom., September, 2023
Disturbance Rejection Using the Combination of Equivalent-Input-Disturbance and Model-Predictive-Control Methods.
Proceedings of the 49th Annual Conference of the IEEE Industrial Electronics Society, 2023
2022
Exploring the characteristics of smart agricultural development in Japan: Analysis using a smart agricultural kaizen level technology map.
Comput. Electron. Agric., 2022
Improving habitability for wind-induced structural vibration by equivalent-input-disturbance approach.
Proceedings of the IECON 2022, 2022
Proceedings of the IEEE/ASME International Conference on Advanced Intelligent Mechatronics, 2022
2021
Proceedings of the IECON 2021, 2021
2018
Proceedings of the 57th IEEE Conference on Decision and Control, 2018
Proceedings of the 2018 Annual American Control Conference, 2018
2017
Dynamic visual feedback position tracking of two-wheeled vehicles with a target vehicle motion model.
Proceedings of the IEEE Conference on Control Technology and Applications, 2017
2015
Three-MLP Ensemble Re-RX algorithm and recent classifiers for credit-risk evaluation.
Proceedings of the 2015 International Joint Conference on Neural Networks, 2015
Stochastic performance analysis of visual motion observer and experimental verifications.
Proceedings of the 10th Asian Control Conference, 2015
2012
ACM Trans. Design Autom. Electr. Syst., 2012
Proceedings of the 13th ACIS International Conference on Software Engineering, 2012
2007
Automatic classification of spinal deformity by using four symmetrical features on the moire images.
Proceedings of the Artificial Neural Networks and Intelligent Information Processing, 2007
2004
A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory.
IEEE J. Solid State Circuits, 2004