Satoshi Komatsu

According to our database, Satoshi Komatsu authored at least 51 papers between 1998 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

A PVT Variation Dependencies of VCO in Frequency Locked Loop.

Kota Hara, Satoshi Komatsu

Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2018

A Framework for Automatic Generation of Fully Synthesizable ADPLL.

Shinya Ubukata, Satoshi Komatsu

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017

Characteristics optimization of stochastic ADC and its automatic generation system.

Ryosuke Yumoto, Satoshi Komatsu

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

A low-voltage hysteresis comparator for low power applications.

Takumi Saito, Satoshi Komatsu

Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2016

Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing.

Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada

IEICE Trans. Electron., 2016

Dynamic Power Integrity Control of ATE for Eliminating Overkills and Underkills in Device Testing.

Masahiro Ishida, Toru Nakura, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada

J. Electron. Test., 2016

A comparative study of body biased time-to-digital converters based on stochastic arbiters and stochastic comparators.

James S. Tandon, Satoshi Komatsu, Takahiro J. Yamaguchi, Kunihiro Asada

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

2014

A Flash TDC with 2.6-4.2ps Resolution Using a Group of UnbalancedCMOS Arbiters.

Satoshi Komatsu, Takahiro J. Yamaguchi, Mohamed Abbas, Nguyen Ngoc Mai Khanh, James S. Tandon, Kunihiro Asada

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing.

Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Statistical silicon results of dynamic power integrity control of ATE for eliminating overkills and underkills.

Masahiro Ishida, Takashi Kusaka, Toru Nakura, Satoshi Komatsu, Kunihiro Asada

Proceedings of the 2014 International Test Conference, 2014

A subsampling stochastic coarse-fine ADC with SNR 55.3dB and >5.8TS/s effective sample rate for an on-chip signal analyzer.

James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A Novel Circuit for Transition-Edge Detection: Using a Stochastic Comparator Group to Test Transition-Edge.

Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters.

Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

A novel test structure for measuring the threshold voltage variance in MOSFETs.

Takahiro J. Yamaguchi, James S. Tandon, Satoshi Komatsu, Kunihiro Asada

Proceedings of the 2013 IEEE International Test Conference, 2013

A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection.

Rimon Ikeno, Takashi Maruyama, Satoshi Komatsu, Tetsuya Iizuka, Makoto Ikeda, Kunihiro Asada

Proceedings of the International Symposium on Physical Design, 2013

A stochastic sampling time-to-digital converter with tunable 180-770fs resolution, INL less than 0.6LSB, and selectable dynamic range offset.

James S. Tandon, Takahiro J. Yamaguchi, Satoshi Komatsu, Kunihiro Asada

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design.

Rimon Ikeno, Takashi Maruyama, Tetsuya Iizuka, Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Power integrity control of ATE for emulating power supply fluctuations on customer environment.

Masahiro Ishida, Toru Nakura, Toshiyuki Kikkawa, Takashi Kusaka, Satoshi Komatsu, Kunihiro Asada

Proceedings of the 2012 IEEE International Test Conference, 2012

A New Procedure for Measuring High-Accuracy Probability Density Functions.

Takahiro J. Yamaguchi, Kunihiro Asada, Kiichi Niitsu, Mohamed Abbas, Satoshi Komatsu, Haruo Kobayashi, Jose A. Moreira

Proceedings of the 21st IEEE Asian Test Symposium, 2012

2011

Application of a continuous-time level crossing quantization method for timing noise measurements.

Takahiro J. Yamaguchi, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Kunihiro Asada, Mohamed Abbas, Satoshi Komatsu

Proceedings of the 2011 IEEE International Test Conference, 2011

An equivalent-time and clocked approach for continuous-time quantization.

Takahiro J. Yamaguchi, Mohamed Abbas, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Satoshi Komatsu, Kunihiro Asada

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Novel technique for minimizing the comparator delay dispersion in 65nm CMOS technology.

Mohamed Abbas, Takahiro J. Yamaguchi, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010

An automatic test generation framework for digitally-assisted adaptive equalizers in high-speed serial links.

Mohamed Abbas, Kwang-Ting Cheng, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Interconnect-Aware Pipeline Synthesis for Array-Based Architectures.

Shanghua Gao, Hiroaki Yoshida, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Signature-Based Testing for Digitally-Assisted Adaptive Equalizers in High-Speed Serial Links.

Mohamed Abbas, Kwang-Ting Cheng, Yasuo Furukawa, Satoshi Komatsu, Kunihiro Asada

Proceedings of the 14th IEEE European Test Symposium, 2009

SAT-based ATPG testing of inter- and intra-gate bridging faults.

Toru Nakura, Yutaro Tatemura, Görschwin Fey, Makoto Ikeda, Satoshi Komatsu, Kunihiro Asada

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008

VLSI Test Exercise Courses for Students in EE Department.

Satoshi Komatsu

Proceedings of the 2008 IEEE International Test Conference, 2008

Targeting Leakage Constraints during ATPG.

Görschwin Fey, Satoshi Komatsu, Yasuo Furukawa, Masahiro Fujita

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

VLSI CAD Education and Exercise Course with Public Domain Tools.

Satoshi Komatsu, Kazuyoshi Takagi, Masahiro Fujita, Kunihiro Asada

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

Interconnect-aware Pipeline Synthesis for Array based Reconfigurable Architectures.

Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita

Proceedings of the Embedded System Design: Topics, Techniques and Trends, IFIP TC10 Working Conference: International Embedded Systems Symposium (IESS), May 30, 2007

Using Counterexample Analysis to Minimize the Number of Predicates for Predicate Abstraction.

Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita

Proceedings of the Automated Technology for Verification and Analysis, 2007

Protocol Transducer Synthesis using Divide and Conquer approach.

Shigeru Watanabe, Kenshu Seto, Yuji Ishikawa, Satoshi Komatsu, Masahiro Fujita

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Synchronization Verification in System-Level Design with ILP Solvers.

Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

The AMS Extension to System Level Design Language - SpecC.

Yu Liu, Satoshi Komatsu, Masahiro Fujita

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

Synchronization Mechanism for Timed/Untimed Mixed-Signal System Level Design Environment.

Yu Liu, Satoshi Komatsu, Masahiro Fujita

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

An optimization of bus interconnects pitch for low-power and reliable bus encoding scheme.

Satoshi Komatsu, Masahiro Fujita

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Dynamically reconfigurable protocol transducer.

Shota Watanabe, Yuji Ishikawa, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

2005

Low Power and Fault Tolerant Encoding Methods for On-Chip Data Transfer in Practical Applications.

Satoshi Komatsu, Masahiro Fujita

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

System level design language extensions for timed/untimed digital-analog combined system design.

Yu Liu, Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Pipeline Scheduling for Array Based Reconfigurable Architectures Considering Interconnect Delays.

Shanghua Gao, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

AMS Extensions for Timed/Untimed System-Level Design Language.

Yu Liu, Satoshi Komatsu, Masahiro Fujita

Proceedings of the Forum on specification and Design Languages, 2005

2003

Verification of Synchronization in SpecC Description with the Use of Difference Decision Diagrams.

Thanyapat Sakunkonchak, Satoshi Komatsu, Masahiro Fujita

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks.

Satoshi Komatsu, Masahiro Fujita

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Comparative Study On Verilog-Based And C-Based Hardware Design Education.

Tohru Ishihara, Satoshi Komatsu, Makoto Ikeda, Masahiro Fujita, Kunihiro Asada

Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Engineering Changes in Field Modifiable Architectures.

Hiroshi Saito, Kenshu Seto, Yoshihisa Kojima, Satoshi Komatsu, Masahiro Fujita

Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003

Field Modifiable Architecture with FPGAs and its Design/Verification/Debugging Methodologies.

Masahiro Fujita, Satoshi Komatsu, Hiroshi Saito, Kenshu Seto, Thanyapat Sakunkonchak, Yoshihisa Kojima

Proceedings of the 36th Hawaii International Conference on System Sciences (HICSS-36 2003), 2003

Irredundant address bus encoding techniques based on adaptive codebooks for low power.

Satoshi Komatsu, Masahiro Fujita

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis.

Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita

Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Field modifiable architecture with FPGAs and its design methodology.

Satoshi Komatsu, Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Masahiro Fujita

Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

1999

Low Power Chip Interface Based on Bus Data Encoding with Adaptive Code-Book Method.

Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998

Low Power Micoprocessors for Comparative Study on Bus Architecture and Multiplexer Architecture.

Satoshi Komatsu, Makoto Ikeda, Kunihiro Asada

Proceedings of the ASP-DAC '98, 1998