Satoshi Kawakami

Orcid: 0000-0001-5044-744X

Affiliations:
  • Kyushu University, Fukuoka, Japan


According to our database1, Satoshi Kawakami authored at least 17 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2024
Open-Source Silicon - Unleashing Innovation and Collaboration.
IEEE Des. Test, December, 2024

Late Breaking Results: Single Flux Quantum Based Brownian Circuits for Ultra-Law-Power Computing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
Empirical Power-performance Analysis of Layer-wise CNN Inference on Single Board Computers.
J. Inf. Process., 2023

Design of The Ultra-Low-Power Driven VMM Configurations for μW Scale IoT Devices.
Proceedings of the 16th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2023

Evaluating floating-point multipliers with opto-electrical hybrid circuits.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

2022
An Edge Autonomous Lamp Control with Camera Feedback.
Proceedings of the 8th IEEE World Forum on Internet of Things, 2022

Design and Analysis of a Nano-photonic Processing Unit for Low-Latency Recurrent Neural Network Applications.
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

A Hybrid Opto-Electrical Floating-point Multiplier.
Proceedings of the 15th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2022

Design of Variable Bit-Width Arithmetic Unit Using Single Flux Quantum Device.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Superconductor Computing for Neural Networks.
IEEE Micro, 2021

2020
32 GHz 6.5 mW Gate-Level-Pipelined 4-Bit Processor using Superconductor Single-Flux-Quantum Logic.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

SuperNPU: An Extremely Fast Neural Processing Unit Using Superconducting Logic Devices.
Proceedings of the 53rd Annual IEEE/ACM International Symposium on Microarchitecture, 2020

Practical Error Modeling Toward Realistic NISQ Simulation.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

How Many Trials Do We Need for Reliable NISQ Computing?
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Enhancing a manycore-oriented compressed cache for GPGPU.
Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2020

2018
Parallel Precomputation with Input Value Prediction for Model Predictive Control Systems.
IEICE Trans. Inf. Syst., 2018

2013
Many-core acceleration for model predictive control systems.
Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, 2013


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