Satoshi Kaneko
According to our database1,
Satoshi Kaneko
authored at least 16 papers
between 1999 and 2023.
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Bibliography
2023
Proceedings of the International Conference on Software, 2023
2022
A SYCL-based high-level programming framework for HPC programmers to use remote FPGA clusters.
Proceedings of the HEART 2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba, Japan, June 9, 2022
Fundamental Study of Neonate Fingerprint Recognition Using Fingerprint Classification.
Proceedings of the 21st International Conference of the Biometrics Special Interest Group, 2022
2021
Application of Reversible Data Hiding for Printing with Special Color Inks to Preserve Compatibility with Normal Printing.
CoRR, 2021
2020
Estimation of Layered Ink Layout to reproduce desired Translucency of skin in Inkjet 3D Printer using deep neural network trained with synthetic simulated data.
Proceedings of the 28th Color and Imaging Conference, 2020
2019
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019
Estimation of Layered Ink Layout from Arbitrary Skin Color and Translucency in Inkjet 3D Printer.
Proceedings of the 27th Color and Imaging Conference, 2019
Development of 2,400ppi Fingerprint Sensor for Capturing Neonate Fingerprint within 24 Hours after Birth.
Proceedings of the 2019 International Conference of the Biometrics Special Interest Group, 2019
2017
Indirect Periodic Disturbance Compensator using Feedforward Control for Image Noises.
Proceedings of the Color Imaging XXII: Displaying, 2017
2013
25 Gb/s 150-m Multi-Mode Fiber Transmission Using a CMOS-Driven 1.3-µm Lens-Integrated Surface-Emitting Laser.
IEICE Trans. Electron., 2013
2011
Proceedings of the Learning and Intelligent Optimization - 5th International Conference, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2008
Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors.
IEEE J. Solid State Circuits, 2008
Evaluation and Improvement of Digital Watermarking Algorithm Based on Cryptographic Security Models.
Proceedings of the Digital Watermarking, 7th International Workshop, 2008
2004
A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory.
IEEE J. Solid State Circuits, 2004
1999
Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999