Satoshi Imamura

Orcid: 0000-0002-8703-3264

According to our database1, Satoshi Imamura authored at least 23 papers between 1992 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2024
C3-VQA: Cryogenic Counter-based Co-processor for Variational Quantum Algorithms.
CoRR, 2024

SFQ counter-based precomputation for large-scale cryogenic VQE machines.
CoRR, 2024

2023
mpiQulacs: A Scalable Distributed Quantum Computer Simulator for ARM-based Clusters.
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2023

Offline Quantum Circuit Pruning for Quantum Chemical Calculations.
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2023

Accelerating Multilingual Applications with In-memory Array Sharing.
Proceedings of the IEEE International Conference on Big Data, 2023

2022
Plush: A Write-Optimized Persistent Log-Structured Hash-Table.
Proc. VLDB Endow., 2022

mpiQulacs: A Distributed Quantum Computer Simulator for A64FX-based Cluster Systems.
CoRR, 2022

2021
Cost-Performance Evaluation of Heterogeneous Tierless Storage Management in a Public Cloud.
Proceedings of the Ninth International Symposium on Computing and Networking, 2021

2020
Mosaic: A Budget-Conscious Storage Engine for Relational Database Systems.
Proc. VLDB Endow., 2020

FairHym: Improving Inter-Process Fairness on Hybrid Memory Systems.
Proceedings of the 9th Non-Volatile Memory Systems and Applications Symposium, 2020

2019
Japanese Lexical Variation Explained by Spatial Contact Patterns.
ISPRS Int. J. Geo Inf., 2019

Reducing CPU Power Consumption with Device Utilization-Aware DVFS for Low-Latency SSDs.
IEICE Trans. Inf. Syst., 2019

POSTER: AR-MMAP: Write Performance Improvement of Memory-Mapped File.
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2018
Evaluating Energy-Efficiency of DRAM Channel Interleaving Schemes for Multithreaded Programs.
IEICE Trans. Inf. Syst., 2018

Reducing CPU Power Consumption for Low-Latency SSDs.
Proceedings of the IEEE 7th Non-Volatile Memory Systems and Applications Symposium, 2018

2016
Power-Efficient Breadth-First Search with DRAM Row Buffer Locality-Aware Address Mapping.
Proceedings of the 2016 High Performance Graph Data Management and Processing Workshop, 2016

Evaluating the impacts of code-level performance tunings on power efficiency.
Proceedings of the 2016 IEEE International Conference on Big Data (IEEE BigData 2016), 2016

2014
Influence of Information Structure on Word Order Change and Topic Marker WA in Japanese.
Proceedings of the 28th Pacific Asia Conference on Language, Information and Computation, 2014

The Influence of Givenness and Heaviness on OSV in Japanese.
Proceedings of the 28th Pacific Asia Conference on Language, Information and Computation, 2014

Power-capped DVFS and thread allocation with ANN models on modern NUMA systems.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013
Coordinated power-performance optimization in manycores.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2007
Vision Recognition System by Using Chaotic Search.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

1992
FDL: A Constraint Based Object Oriented Language for Functional Design.
Proceedings of the Human Aspects in Computer Integrated Manufacturing, 1992


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