Satoru Takase

According to our database1, Satoru Takase authored at least 4 papers between 1993 and 2014.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

1995
2000
2005
2010
0
1
2
1
1
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2014
A 130.7-mm<sup>2</sup> 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology.
IEEE J. Solid State Circuits, 2014

2013

1999
A 1.6-GByte/s DRAM with flexible mapping redundancy technique and additional refresh scheme.
IEEE J. Solid State Circuits, 1999

1993
A 500-megabyte/s data-rate 4.5 M DRAM.
IEEE J. Solid State Circuits, April, 1993


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