Satish Maheshwaram

According to our database, Satish Maheshwaram authored at least 11 papers between 2010 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Performance analysis of geometric variations in circular double gate MOSFETs at sub-7nm technology nodes.

Kallepelli Sagar, Satish Maheshwaram, Vadthiya Narendar

Microelectron. J., December, 2023

NDR free negative capacitance CGAAFET at 2nm technology node for low power and high-speed applications.

Ravi Kothapally, Vadthiya Narendar, Satish Maheshwaram

Microelectron. J., December, 2023

2022

Emerging Two Dimensional Channel Materials for MOSFETs: A Review.

Rudravaram Srikanth, Satish Maheshwaram

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

Performance Comparison of Circular Double Gate Transistor (CDGT) with Novel Architectures for High-Performance Applications.

Kallepelli Sagar, Satish Maheshwaram

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

Impact on the Performance of North Bridge I/O Peripheral Component Interconnect Express Block in Physical Design Flow Considering Two Different Synthesis Corners at below 10nm Technology Node.

Neha Karna, Jagannadha Rao Arisankula, Satish Maheshwaram

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

Resistive Calibrated Zero Temperature Coefficient Band Gap Reference (BGR).

Nikita Dindhoria, G. S. Rohit Reddy, Satish Maheshwaram

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2017

Vertical Nanowire FET Based Standard Cell Design Employing Verilog-A Compact Model for Higher Performance.

Satish Maheshwaram, Om. Prakash, Mohit Sharma, Anand Bulusu, Sanjeev Manhas

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2016

A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation.

Om. Prakash, Satish Maheshwaram, Mohit Sharma, Anand Bulusu, A. K. Saxena, S. K. Manhas

Proceedings of the 20th International Symposium on VLSI Design and Test, 2016

Lateral silicon nanowire based standard cell design for higher performance.

Om. Prakash, Mohit Sharma, Anand Bulusu, A. K. Saxena, S. K. Manhas, Satish Maheshwaram

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015

Low power SRAM design for 14 nm GAA Si-nanowire technology.

Gaurav Kaushal, H. Jeong, Satish Maheshwaram, S. K. Manhas, Sudeb Dasgupta, Seong-Ook Jung

Microelectron. J., 2015

2010

A high performance vertical Si nanowire CMOS for ultra high density circuits.

Satish Maheshwaram, Gaurav Kaushal, S. K. Manhas

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010