Sassan Tabatabaei

According to our database1, Sassan Tabatabaei authored at least 25 papers between 1997 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2020
3.7 A 620µW BJT-Based Temperature-to-Digital Converter with 0.65mK Resolution and FoM of 190fJ·K<sup>2</sup>.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2017
A MEMS-Assisted Temperature Sensor With 20-µK Resolution, Conversion Rate of 200 S/s, and FOM of 0.04 pJK2.
IEEE J. Solid State Circuits, 2017

2016
11.1 Dual-MEMS-resonator temperature-to-digital converter with 40 K resolution and FOM of 0.12pJK2.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

2013
A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With < ±0.5-ppm Frequency Stability and < 1-ps Integrated Jitter.
IEEE J. Solid State Circuits, 2013

2012
A temperature-to-digital converter for a MEMS-based programmable oscillator with better than ±0.5ppm frequency stability.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2010
Silicon MEMS Oscillators for High-Speed Digital Systems.
IEEE Micro, 2010

2007
Design of a Tunable Differential Ring Oscillator With Short Start-Up and Switching Transients.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

2005
Crosstalk bounded uncorrelated jitter (BUJ) for high-speed interconnects.
IEEE Trans. Instrum. Meas., 2005

A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices.
J. Electron. Test., 2005

Jitter spectrum analysis using continuous time interval analyzer (CTIA).
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

A DDJ calibration methodology for high-speed test and measurement equipments.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004
Jitter Models for the Design and Test of Gbps-Speed Serial Interconnects.
IEEE Des. Test Comput., 2004

Jitter Generation and Measurement for Test of Multigbps Serial IO.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Jitter Models and Measurement Methods for High-Speed Serial Interconnects.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs.
IEEE Des. Test Comput., 2003

Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
Embedded Timing Analysis: A SoC Infrastructure.
IEEE Des. Test Comput., 2002

Analog and Mixed Signal BIST: Too Much, Too Little, Too Late?
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Multi-GigaHertz Testing Challenges and Solutions.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

An Embedded Core for Sub-Picosecond Timing Measurements.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2000
Defect Oriented Testing of an ECL/CMOS Level Converter Circuit.
Proceedings of the 1st Latin American Test Workshop, 2000

1999
A Current Integrator for BIST of Mixed-Signal ICs.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

A built-in current monitor for testing analog circuit blocks.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
Testing for Floating Gates Defects in CMOS Circuits.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997
Power supply current monitoring techniques for testing PLLs.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997


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