Sasindu Wijeratne

According to our database, Sasindu Wijeratne authored at least 17 papers between 2017 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

PAHD: Perception-Action based Human Decision Making using Explainable Graph Neural Networks on SAR Images.

Sasindu Wijeratne, Bingyi Zhang, Rajgopal Kannan, Viktor K. Prasanna, Carl E. Busart

CoRR, 2024

Sparse MTTKRP Acceleration for Tensor Decomposition on GPU.

Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna

Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024

2023

Graph Neural Network for Accurate and Low-complexity SAR ATR.

Bingyi Zhang, Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna, Carl E. Busart

CoRR, 2023

Dynasor: A Dynamic Memory Layout for Accelerating Sparse MTTKRP for Tensor Decomposition on Multi-core CPU.

Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna

Proceedings of the 35th IEEE International Symposium on Computer Architecture and High Performance Computing, 2023

Exploiting On-Chip Heterogeneity of Versal Architecture for GNN Inference Acceleration.

Paul Chen, Pavan Manjunath, Sasindu Wijeratne, Bingyi Zhang, Viktor K. Prasanna

Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Accelerating Sparse MTTKRP for Tensor Decomposition on FPGA.

Sasindu Wijeratne, Ta-Yang Wang, Rajgopal Kannan, Viktor K. Prasanna

Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

2022

Estimating the Impact of Communication Schemes for Distributed Graph Processing.

Tian Ye, Sanmukh R. Kuppannagari, César A. F. De Rose, Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna

Proceedings of the 21st International Symposium on Parallel and Distributed Computing, 2022

Modeling the Energy Efficiency of GEMM using Optical Random Access Memory.

Bingyi Zhang, Akhilesh R. Jaiswal, Clynn Mathew, Ravi Teja Lakkireddy, Ajey P. Jacob, Sasindu Wijeratne, Viktor K. Prasanna

Proceedings of the IEEE High Performance Extreme Computing Conference, 2022

Performance Modeling Sparse MTTKRP Using Optical Static Random Access Memory on FPGA.

Sasindu Wijeratne, Akhilesh R. Jaiswal, Ajey P. Jacob, Bingyi Zhang, Viktor K. Prasanna

Proceedings of the IEEE High Performance Extreme Computing Conference, 2022

Towards Programmable Memory Controller for Tensor Decomposition.

Sasindu Wijeratne, Ta-Yang Wang, Rajgopal Kannan, Viktor K. Prasanna

Proceedings of the 11th International Conference on Data Science, 2022

2021

Reconfigurable co-processor architecture with limited numerical precision to accelerate deep convolutional neural networks.

Sasindu Wijeratne, Sandaruwan Jayaweera, Mahesh Dananjaya, Ajith Pasqual

CoRR, 2021

Reconfigurable Low-latency Memory System for Sparse Matricized Tensor Times Khatri-Rao Product on FPGA.

Sasindu Wijeratne, Rajgopal Kannan, Viktor K. Prasanna

Proceedings of the 2021 IEEE High Performance Extreme Computing Conference, 2021

Programmable FPGA-based Memory Controller.

Sasindu Wijeratne, Sanket Pattnaik, Zhiyu Chen, Rajgopal Kannan, Viktor K. Prasanna

Proceedings of the IEEE Symposium on High-Performance Interconnects, 2021

2020

A High Throughput Parallel Hash Table on FPGA using XOR-based Memory.

Ruizhi Zhang, Sasindu Wijeratne, Yang Yang, Sanmukh R. Kuppannagari, Viktor K. Prasanna

Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020

2019

Scalable High Performance SDN Switch Architecture on FPGA for Core Networks.

Sasindu Wijeratne, Ashen Ekanayake, Sandaruwan Jayaweera, Danuka Ravishan, Ajith Pasqual

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018

Reconfigurable Co-Processor Architecture with Limited Numerical Precision to Accelerate Deep Convolutiosnal Neural Networks.

Sasindu Wijeratne, Sandaruwan Jayaweera, Mahesh Dananjaya, Ajith Pasqual

Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

2017

High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension.

Rishan Senanayake, Namitha Liyanage, Sasindu Wijeratne, Sachille Atapattu, Kasun Athukorala, P. M. K. Tharaka, Geethan Karunaratne, R. M. A. U. Senarath, Ishantha Perera, Ashen Ekanayake, Ajith Pasqual

Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017