Sasank Garikapati
Orcid: 0000-0003-0939-6331
According to our database1,
Sasank Garikapati
authored at least 11 papers
between 2021 and 2024.
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Bibliography
2024
Full-Duplex Receiver With Wideband, High-Power RF Self-Interference Cancellation Based on Capacitor Stacking in Switched-Capacitor Delay Lines.
IEEE J. Solid State Circuits, July, 2024
Doubling Down on Wireless Capacity: A Review of Integrated Circuits, Systems, and Networks for Full Duplex.
Proc. IEEE, May, 2024
Passive Frequency Shifting of N-Path Filters Through Rotary Clocking: Analysis and Design.
IEEE Trans. Circuits Syst. I Regul. Pap., January, 2024
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024
Proceedings of the 30th Annual International Conference on Mobile Computing and Networking, 2024
2023
A Third-Order Quasi-Elliptic N-Path Filter With Enhanced Linearity Through Clock Boosting.
IEEE J. Solid State Circuits, December, 2023
Proceedings of the ACM SIGCOMM 2023 Conference, 2023
A 1-to-5GHz All-Passive Frequency-Translational 4<sup>th</sup>-Order N-path Filter with Low-Power Clock Boosting for High Linearity and Relaxed $\mathrm{P}_{\text{dc}}$-Frequency Trade-Off.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2021
A Survey and Quantitative Evaluation of Integrated Circuit-Based Antenna Interfaces and Self-Interference Cancellers for Full-Duplex.
IEEE Open J. Commun. Soc., 2021
A Full-Duplex Receiver With True-Time-Delay Cancelers Based on Switched-Capacitor-Networks Operating Beyond the Delay-Bandwidth Limit.
IEEE J. Solid State Circuits, 2021
6.6 Full-Duplex Receiver with Wideband Multi-Domain FIR Cancellation Based on Stacked-Capacitor, N-Path Switched-Capacitor Delay Lines Achieving >54dB SIC Across 80MHz BW and >15dBm TX Power-Handling.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021