Sarwono Sutikno

Orcid: 0000-0002-7755-7240

According to our database1, Sarwono Sutikno authored at least 12 papers between 1994 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Detecting Unknown Hardware Trojans in Register Transfer Level Leveraging Verilog Conditional Branching Features.
IEEE Access, 2023

2022
Trust-Hub Trojan Benchmark for Hardware Trojan Detection Model Creation using Machine Learning.
Dataset, September, 2022

2021
Efficient Machine Learning Model for Hardware Trojan Detection on Register Transfer Level.
Proceedings of the 4th International Conference on Signal Processing and Information Security, 2021

2019
General Model for Secure Electronic Cash Scheme.
Int. J. Netw. Secur., 2019

2018
Design of an AES Device as Device Under Test in a DPA Attack.
Int. J. Netw. Secur., 2018

Attacking AES-Masking Encryption Device with Correlation Power Analysis.
Int. J. Commun. Networks Inf. Secur., 2018

2010
The New Embedded System Design Methodology For Improving Design Process Performance
CoRR, 2010

2009
The New Block Cipher: BC2.
Int. J. Netw. Secur., 2009

Transaction Level Modeling for Early Verification on Embedded System Design.
Proceedings of the 8th IEEE/ACIS International Conference on Computer and Information Science, 2009

2002
VHDL design and simulation of MAM memory for LAPCAM parallel architecture for image processing.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2000
An architecture of F(2<sup>2N</sup>) multiplier for elliptic curves cryptosystem.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1994
A Distributed Reconfiguration Controller for Linear Array Harvest Problem: Hierarchically Quasi-Normalized Neural Approach.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994


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