Sarvesh H. Kulkarni

According to our database, Sarvesh H. Kulkarni authored at least 14 papers between 2003 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

A 0.9-μm² 1T1R Bit Cell in 14-nm High-Density Metal Fuse Technology for High-Volume Manufacturing and In-Field Programming.

Zhanping Chen, Sarvesh H. Kulkarni, Vincent E. Dorgan, Salil Manohar Rajarshi, Lei Jiang, Uddalak Bhattacharya

IEEE J. Solid State Circuits, 2017

2016

A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS.

Sarvesh H. Kulkarni, Zhanping Chen, Balaji Srinivasan, Brian Pedersen, Uddalak Bhattacharya, Kevin Zhang

IEEE J. Solid State Circuits, 2016

A 0.9um² 1T1R bit cell in 14nm SoC process for metal-fuse OTP array with hierarchical bitline, bit level redundancy, and power gating.

Zhanping Chen, Sarvesh H. Kulkarni, Vincent E. Dorgan, Uddalak Bhattacharya, Kevin Zhang

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015

Low-voltage metal-fuse technology featuring a 1.6V-programmable 1T1R bit cell with an integrated 1V charge pump in 22nm tri-gate process.

Sarvesh H. Kulkarni, Zhanping Chen, Balaji Srinivasan, Brian Pedersen, Uddalak Bhattacharya, Kevin Zhang

Proceedings of the Symposium on VLSI Circuits, 2015

2010

A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 μ m ² <i>1T1R</i> Bit Cell in 32 nm High-k Metal-Gate CMOS.

Sarvesh H. Kulkarni, Zhanping Chen, Jun He, Lei Jiang, Brian Pedersen, Kevin Zhang

IEEE J. Solid State Circuits, 2010

2008

Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias.

Sarvesh H. Kulkarni, Dennis Sylvester, David T. Blaauw

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A 1.1 GHz 12 µA/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications.

Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Zhanping Chen, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Ying Zhang, Kevin Zhang, Mark Bohr

IEEE J. Solid State Circuits, 2008

2007

A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications.

Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Yih Zhang, Kevin Zhang, Mark Bohr

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006

Power Distribution Techniques for Dual VDD Circuits.

Sarvesh H. Kulkarni, Dennis Sylvester

J. Low Power Electron., 2006

A statistical framework for post-silicon tuning through body bias clustering.

Sarvesh H. Kulkarni, Dennis Sylvester, David T. Blaauw

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2004

High performance level conversion for dual V_DD design.

Sarvesh H. Kulkarni, Dennis Sylvester

IEEE Trans. Very Large Scale Integr. Syst., 2004

A new algorithm for improved VDD assignment in low power dual VDD systems.

Sarvesh H. Kulkarni, Ashish Srivastava, Dennis Sylvester

Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

2003

An Implementation of a 32-bit ARM Processor Using Dual Power Supplies and Dual Threshold Voltages.

Robert Bai, Sarvesh H. Kulkarni, Wesley Kwong, Ashish Srivastava, Dennis Sylvester, David T. Blaauw

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Pushing ASIC performance in a power envelope.

Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni

Proceedings of the 40th Design Automation Conference, 2003