Saroja V. Siddamal

Orcid: 0000-0002-9579-9980

According to our database1, Saroja V. Siddamal authored at least 13 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of six.

Timeline

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Bibliography

2024
2×VDD IO buffer with 1×VDD devices considering hot-carrier and gate-oxide reliability issues.
Integr., 2024

2023
Supply Noise and Peak Current Reduction in High-Speed Output Drivers.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023

2022
Mixed-Voltage I/O Buffer Using NMOS Blocking Considering Gate Oxide Reliability.
J. Circuits Syst. Comput., 2022

Differential receiver with 2 × VDD input signals using 1 × VDD devices.
Integr., 2022

2021
High Voltage Receiver Using Low Voltage Devices With Reduced Dead-zone.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

$2 \times \text{VDD}$ Tolerant I/O with Considerations of Hot-Carrier Degradation and Gate-Oxide Reliability.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

Novel Gate Tracking and N-well Control Circuit for $2\times \text{VDD}$ Tolerant I/O Buffer.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021

2020
Design and Implementation of chaotic nondeterministic random seed-based Hybrid True Random Number Generator.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

2019
Ultra Low Power Low Frequency On-chip Oscillator for Elapsed Time Counter.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Design and Physical Implementation of Mixed Signal Elapsed Time Counter in 0.18 µm CMOS Technology.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

2018
Development of Data Acquisition System using non-invasive Hardware and 3D software for Electric all terrain Vehicle.
Proceedings of the 2018 International Conference on Advances in Computing, 2018

2014
Design and Implementation of High Throughput and Area Efficient Hard Decision Viterbi Decoder in 65nm Technology.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014

2008
Design of High-Speed Floating Point Multiplier.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008


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