Saroj Satapathy

According to our database, Saroj Satapathy authored at least 6 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Advancing Low-Voltage Complementary Reconfigurable Field-Effect Transistor Operation with Reduced Schottky Barriers.

Juhan Ahn, Saroj Satapathy, Jaydeep P. Kulkarni

Proceedings of the Device Research Conference, 2024

2022

Aging Effects On Clock Gated Memory Phase Paths.

Amlan Ghosh, Saroj Satapathy, Jaydeep P. Kulkarni, Prashant D. Joshi

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

2016

Soft Response Generation and Thresholding Strategies for Linear and Feed-Forward MUX PUFs.

Chen Zhou, Saroj Satapathy, Yingjie Lao, Keshab K. Parhi, Chris H. Kim

Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Estimating delay differences of arbiter PUFs using silicon data.

S. V. Sandeep Avvaru, Chen Zhou, Saroj Satapathy, Yingjie Lao, Chris H. Kim, Keshab K. Parhi

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

A revolving reference odometer circuit for BTI-induced frequency fluctuation measurements under fast DVFS transients.

Saroj Satapathy, Won Ho Choi, Xiaofei Wang, Chris H. Kim

Proceedings of the IEEE International Reliability Physics Symposium, 2015

2014

A test circuit based on a ring oscillator array for statistical characterization of Plasma-Induced Damage.

Won Ho Choi, Saroj Satapathy, John Keane, Chris H. Kim

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014