Sari Onaissi

According to our database, Sari Onaissi authored at least 5 papers between 2008 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2012

Efficient Block-Based Parameterized Timing Analysis Covering All Potentially Critical Paths.

Khaled R. Heloue, Sari Onaissi, Farid N. Najm

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011

A fast approach for static timing analysis covering all PVT corners.

Sari Onaissi, Feroze Taraporevala, Jinfeng Liu, Farid N. Najm

Proceedings of the 48th Design Automation Conference, 2011

2009

PSTA-based branch and bound approach to the silicon speedpath isolation problem.

Sari Onaissi, Khaled R. Heloue, Farid N. Najm

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Clock skew optimization via wiresizing for timing sign-off covering all process corners.

Sari Onaissi, Khaled R. Heloue, Farid N. Najm

Proceedings of the 46th Design Automation Conference, 2009

2008

A Linear-Time Approach for Static Timing Analysis Covering All Process Corners.

Sari Onaissi, Farid N. Najm

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008