Sarath Mohanachandran Nair

According to our database, Sarath Mohanachandran Nair authored at least 18 papers between 2017 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2020

Variation Analysis, Fault Modeling and Yield Improvement of Emerging Spintronic Memories

Sarath Mohanachandran Nair

PhD thesis, 2020

Mitigating Read Failures in STT-MRAM.

Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis.

Rajendra Bishnoi, Lizhou Wu, Moritz Fieback, Christopher Münch, Sarath Mohanachandran Nair, Mehdi Baradaran Tahoori, Ying Wang, Huawei Li, Said Hamdioui

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Physics based modeling of bimodal electromigration failure distributions and variation analysis for VLSI interconnects.

Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi B. Tahoori, Houman Zahedmanesh, Kristof Croes, Kevin Garello, Gouri Sankar Kar, Francky Catthoor

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Defect Characterization and Test Generation for Spintronic-based Compute-In-Memory.

Sarath Mohanachandran Nair, Christopher Münch, Mehdi Baradaran Tahoori

Proceedings of the IEEE European Test Symposium, 2020

A Universal Spintronic Technology based on Multifunctional Standardized Stack.

Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Lionel Torres, Sophiane Senni, Guillaume Patrigeon, Pascal Benoit, Gregory di Pendina, Guillaume Prenat

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Dynamic Faults based Hardware Trojan Design in STT-MRAM.

Sarath Mohanachandran Nair, Rajendra Bishnoi, Arunkumar Vijayan, Mehdi Baradaran Tahoori

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

A Comprehensive Framework for Parametric Failure Modeling and Yield Analysis of STT-MRAM.

Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori

IEEE Trans. Very Large Scale Integr. Syst., 2019

A Spintronics Memory PUF for Resilience Against Cloning Counterfeit.

Samir Ben Dodo, Rajendra Bishnoi, Sarath Mohanachandran Nair, Mehdi Baradaran Tahoori

IEEE Trans. Very Large Scale Integr. Syst., 2019

Variation-Aware Physics-Based Electromigration Modeling and Experimental Calibration for VLSI Interconnects.

Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, Houman Zahedmanesh, Kristof Croes, Kevin Garello, Gouri Sankar Kar, Francky Catthoor

Proceedings of the IEEE International Reliability Physics Symposium, 2019

Variation-aware Fault Modeling and Test Generation for STT-MRAM.

Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, Hayk T. Grigoryan, Grigor Tshagharyan

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

2018

VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool.

Sarath Mohanachandran Nair, Rajendra Bishnoi, Mohammad Saber Golanbari, Fabian Oboril, Fazal Hameed, Mehdi Baradaran Tahoori

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM.

Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, Grigor Tshagharyan, Hayk T. Grigoryan, Gurgen Harutyunyan, Yervant Zorian

Proceedings of the IEEE International Test Conference, 2018

Using multifunctional standardized stack as universal spintronic technology for IoT.

Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Sophiane Senni, Jad Mohdad, Frédérick Mailly, Lionel Torres, Pascal Benoit, Abdoulaye Gamatié, Pascal Nouet, Frederic Ouattara, Gilles Sassatelli, Kotb Jabeur, Pierre Vanhauwaert, A. Atitoaie, I. Firastrau, Gregory di Pendina, Guillaume Prenat

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Parametric failure modeling and yield analysis for STT-MRAM.

Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Process variation and temperature aware adaptive scrubbing for retention failures in STT-MRAM.

Nour Sayed, Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

GREAT: HeteroGeneous IntegRated Magnetic tEchnology Using Multifunctional Standardized sTack.

Mehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, Sophiane Senni, Jad Mohdad, Frédérick Mailly, Lionel Torres, Pascal Benoit, Pascal Nouet, Rui Ma, Martin Kreißig, Frank Ellinger, Kotb Jabeur, Pierre Vanhauwaert, Gregory di Pendina, Guillaume Prenat

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

VAET-STT: A variation aware estimator tool for STT-MRAM based memories.

Sarath Mohanachandran Nair, Rajendra Bishnoi, Mohammad Saber Golanbari, Fabian Oboril, Mehdi Baradaran Tahoori

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017