Sarani Bhattacharya
Orcid: 0000-0002-4190-2671
According to our database1,
Sarani Bhattacharya
authored at least 42 papers
between 2012 and 2024.
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Bibliography
2024
J. Cryptogr. Eng., June, 2024
µLAM: A LLM-Powered Assistant for Real-Time Micro-architectural Attack Detection and Mitigation.
IACR Cryptol. ePrint Arch., 2024
"There's always another counter": Detecting Micro-architectural Attacks in a Probabilistically Interleaved Malicious/Benign Setting.
IACR Cryptol. ePrint Arch., 2024
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024
Proceedings of the Applied Cryptography and Network Security Workshops, 2024
2023
"Whispering MLaaS" Exploiting Timing Channels to Compromise User Privacy in Deep Neural Networks.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023
A practical key-recovery attack on LWE-based key- encapsulation mechanism schemes using Rowhammer.
IACR Cryptol. ePrint Arch., 2023
Uncovering Vulnerabilities in Smartphone Cryptography: A Timing Analysis of the Bouncy Castle RSA Implementation.
IACR Cryptol. ePrint Arch., 2023
CoRR, 2023
Are Randomized Caches Truly Random? Formal Analysis of Randomized-Partitioned Caches.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023
2022
CoRR, 2022
Timed speculative attacks exploiting store-to-load forwarding bypassing cache-based countermeasures.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
Proceedings of the 2022 Workshop on Attacks and Solutions in Hardware Security, 2022
2021
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021
Victims Can Be Saviors: A Machine Learning-based Detection for Micro-Architectural Side-Channel Attacks.
ACM J. Emerg. Technol. Comput. Syst., 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
IEEE Trans. Computers, 2020
IACR Cryptol. ePrint Arch., 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
IPA: an Instruction Profiling-Based Micro-architectural Side-Channel Attack on Block Ciphers.
J. Hardw. Syst. Secur., 2019
Using Memory Allocation Schemes in Linux to Exploit DRAM Vulnerability: with Rowhammer as a Case Study.
CoRR, 2019
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019
In-situ Extraction of Randomness from Computer Architecture Through Hardware Performance Counters.
Proceedings of the Smart Card Research and Advanced Applications, 2019
2018
ACM Trans. Priv. Secur., 2018
IEEE Embed. Syst. Lett., 2018
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, 2018
2017
Formal fault analysis of branch predictors: attacking countermeasures of asymmetric key ciphers.
J. Cryptogr. Eng., 2017
IACR Cryptol. ePrint Arch., 2017
Performance Counters to Rescue: A Machine Learning based safeguard against Micro-architectural Side-Channel-Attacks.
IACR Cryptol. ePrint Arch., 2017
Tackling the Time-Defence: An Instruction Count Based Micro-architectural Side-Channel Attack on Block Ciphers.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2017
2016
IET Inf. Secur., 2016
IACR Cryptol. ePrint Arch., 2016
Proceedings of the 2016 ACM/IEEE International Conference on Formal Methods and Models for System Design, 2016
A Formal Security Analysis of Even-Odd Sequential Prefetching in Profiled Cache-Timing Attacks.
Proceedings of the Hardware and Architectural Support for Security and Privacy 2016, 2016
2015
Who watches the watchmen? : Utilizing Performance Monitors for Compromising keys of RSA on Intel Platforms.
IACR Cryptol. ePrint Arch., 2015
2014
Fault Attack revealing Secret Keys of Exponentiation Algorithms from Branch Prediction Misses.
IACR Cryptol. ePrint Arch., 2014
2013
2012
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012