Sara Choi
Orcid: 0000-0002-4179-7680
According to our database1,
Sara Choi
authored at least 8 papers
between 2016 and 2022.
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Collaborative distances:
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Bibliography
2022
A 1Tb 3b/Cell 8th-Generation 3D-NAND Flash Memory with 164MB/s Write Throughput and a 2.4Gb/s Interface.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2021
Self-Referenced Single-Ended Resistance Monitoring Write Termination Scheme for STT-RAM Write Energy Reduction.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
2020
IEEE Access, 2020
2019
Offset-Canceling Single-Ended Sensing Scheme With One-Bit-Line Precharge Architecture for Resistive Nonvolatile Memory in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2019
A Decoder for Short BCH Codes With High Decoding Efficiency and Low Power for Emerging Memories.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Offset-Cancellation Sensing-Circuit-Based Nonvolatile Flip-Flop Operating in Near-Threshold Voltage Region.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016