Saptadeep Pal

According to our database, Saptadeep Pal authored at least 15 papers between 2014 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

DeepFlow: A Cross-Stack Pathfinding Framework for Distributed AI Systems.

Newsha Ardalani, Saptadeep Pal, Puneet Gupta

ACM Trans. Design Autom. Electr. Syst., March, 2024

Waferscale Network Switches.

Shuangliang Chen, Saptadeep Pal, Rakesh Kumar

Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

2023

Chiplets: How Small is too Small?

Alexander Graening, Saptadeep Pal, Puneet Gupta

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2021

Scale-Out Packageless Processing

Saptadeep Pal

PhD thesis, 2021

Designing a 2048-Chiplet, 14336-Core Waferscale Processor.

Saptadeep Pal, Jingyang Liu, Irina Alam, Nicholas Cebry, Haris Suhail, Shi Bu, Subramanian S. Iyer, Sudhakar Pamarti, Rakesh Kumar, Puneet Gupta

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

Design Space Exploration for Chiplet-Assembly-Based Processors.

Saptadeep Pal, Daniel Petrisko, Rakesh Kumar, Puneet Gupta

IEEE Trans. Very Large Scale Integr. Syst., 2020

Pathfinding for 2.5D interconnect technologies.

Saptadeep Pal, Puneet Gupta

Proceedings of the SLIP '20: System-Level Interconnect, 2020

2019

Optimizing Multi-GPU Parallelization Strategies for Deep Learning Training.

Saptadeep Pal, Eiman Ebrahimi, Arslan Zulfiqar, Yaosheng Fu, Victor Zhang, Szymon Migacz, David W. Nellans, Puneet Gupta

IEEE Micro, 2019

Compression with multi-ECC: enhanced error resiliency for magnetic memories.

Irina Alam, Saptadeep Pal, Puneet Gupta

Proceedings of the International Symposium on Memory Systems, 2019

Architecting Waferscale Processors - A GPU Case Study.

Saptadeep Pal, Daniel Petrisko, Matthew Tomei, Puneet Gupta, Subramanian S. Iyer, Rakesh Kumar

Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

2018

A Case for Packageless Processors.

Saptadeep Pal, Daniel Petrisko, Adeel Ahmad Bajwa, Puneet Gupta, Subramanian S. Iyer, Rakesh Kumar

Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2018

2017

Advanced Packaging and Heterogeneous Integration to Reboot Computing.

Saptadeep Pal, Subramanian S. Iyer, Puneet Gupta

Proceedings of the IEEE International Conference on Rebooting Computing, 2017

Hybrid VC-MTJ/CMOS non-volatile stochastic logic for efficient computing.

Shaodi Wang, Saptadeep Pal, Tianmu Li, Andrew Pan, Cecile Grezes, Pedram Khalili Amiri, Kang L. Wang, Puneet Gupta

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2014

Cable length minimisation in long-reach-PON planning for sparsely populated areas.

Saptadeep Pal, Cezary Zukowski, Avishek Nag, David B. Payne, Marco Ruffini

Proceedings of the 18th International Conference on Optical Network Design and Modeling, 2014

FPGA implementation of stream cipher using Toeplitz Hash function.

Saptadeep Pal, K. K. Soundra Pandian, Kailash Chandra Ray

Proceedings of the 2014 International Conference on Advances in Computing, 2014