Santosh Pande

Orcid: 0000-0001-6723-8062

Affiliations:
  • Georgia Institute of Technology, Atlanta GA, USA


According to our database1, Santosh Pande authored at least 129 papers between 1990 and 2024.

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Bibliography

2024
Combined Static Analysis and Machine Learning Prediction for Application Debloating.
CoRR, 2024

Improving Program Debloating with 1-DU Chain Minimality.
Proceedings of the 2024 IEEE/ACM 46th International Conference on Software Engineering: Companion Proceedings, 2024

Pythia: Compiler-Guided Defense Against Non-Control Data Attacks.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
Beacons: An End-to-End Compiler Framework for Predicting and Utilizing Dynamic Loop Characteristics.
Proc. ACM Program. Lang., October, 2023

Practical compilation of fexprs using partial evaluation: Fexprs can performantly replace macros in purely-functional Lisp.
CoRR, 2023

PinIt: Influencing OS Scheduling via Compiler-Induced Affinities.
Proceedings of the 24th ACM SIGPLAN/SIGBED International Conference on Languages, 2023

Decker: Attack Surface Reduction via On-Demand Code Mapping.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022
Near-Zero Downtime Recovery From Transient-Error-Induced Crashes.
IEEE Trans. Parallel Distributed Syst., 2022

Compiler-assisted scheduling for multi-instance GPUs.
Proceedings of the GPGPU@PPoPP 2022: Proceedings of the 14th Workshop on General Purpose Processing Using GPU, 2022

CASE: a compiler-assisted SchEduling framework for multi-GPU systems.
Proceedings of the PPoPP '22: 27th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, Seoul, Republic of Korea, April 2, 2022

VICO: demand-driven verification for improving compiler optimizations.
Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022

Com-CAS: Effective Cache Apportioning under Compiler Guidance.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022

2021
Not so fast: understanding and mitigating negative impacts of compiler optimizations on code reuse gadget sets.
Proc. ACM Program. Lang., 2021

On-the-fly Code Activation for Attack Surface Reduction.
CoRR, 2021

Effective GPU Sharing Under Compiler Guidance.
CoRR, 2021

Compiler-Guided Throughput Scheduling for Many-core Machines.
CoRR, 2021

Effective Cache Apportioning for Performance Isolation Under Compiler Guidance.
CoRR, 2021

Distributed Work Stealing at Scale via Matchmaking.
Proceedings of the IEEE International Conference on Cluster Computing, 2021

2020
A Compiler Assisted Scheduler for Detecting and Mitigating Cache-Based Side Channel Attacks.
CoRR, 2020

BlankIt library debloating: getting what you want instead of cutting what you don't.
Proceedings of the 41st ACM SIGPLAN International Conference on Programming Language Design and Implementation, 2020

Generating Robust Parallel Programs via Model Driven Prediction of Compiler Optimizations for Non-determinism.
Proceedings of the ICPP 2020: 49th International Conference on Parallel Processing, 2020

2019
CARVE: Practical Security-Focused Software Debloating Using Simple Feature Set Mappings.
CoRR, 2019

Is Less Really More? Why Reducing Code Reuse Gadget Counts via Software Debloating Doesn't Necessarily Lead to Better Security.
CoRR, 2019

Binary Debloating for Security via Demand Driven Loading.
CoRR, 2019

Is Less Really More? Towards Better Metrics for Measuring Security Improvements Realized Through Software Debloating.
Proceedings of the 12th USENIX Workshop on Cyber Security Experimentation and Test, 2019

CARE: compiler-assisted recovery from soft failures.
Proceedings of the International Conference for High Performance Computing, 2019

Characterizing Dominant Program Behavior Using the Execution-Time Variance of the Call Structure.
Proceedings of the 25th IEEE Real-Time and Embedded Technology and Applications Symposium, 2019

Quantifying and Reducing Execution Variance in STM via Model Driven Commit Optimization.
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2019

2018
LADR: low-cost application-level detector for reducing silent output corruptions.
Proceedings of the 27th International Symposium on High-Performance Parallel and Distributed Computing, 2018

2016
Efficient distributed workstealing via matchmaking.
Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2016

2015
PiMiCo: Privacy Preservation via Migration in Collaborative Mobile Clouds.
Proceedings of the 48th Hawaii International Conference on System Sciences, 2015

Compiler Assisted Load Balancing on Large Clusters.
Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015

2014
F2C2-STM: Flux-Based Feedback-Driven Concurrency Control for STMs.
Proceedings of the 2014 IEEE 28th International Parallel and Distributed Processing Symposium, 2014

Detecting memory leaks through introspective dynamic behavior modelling using machine learning.
Proceedings of the 36th International Conference on Software Engineering, 2014

Automated memory leak detection for production use.
Proceedings of the 36th International Conference on Software Engineering, 2014

DeSTM: harnessing determinism in STMs for application development.
Proceedings of the International Conference on Parallel Architectures and Compilation, 2014

2013
Multiverse: efficiently supporting distributed high-level speculation.
Proceedings of the 2013 ACM SIGPLAN International Conference on Object Oriented Programming Systems Languages & Applications, 2013

2012
Safe compiler-driven transaction checkpointing and recovery.
Proceedings of the 27th Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2012

Hybrid Transactions: Lock Allocation and Assignment for Irrevocability.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012

2011
Compiler-Supported Thread Management for Multithreaded Network Processors.
ACM Trans. Embed. Comput. Syst., 2011

Brainy: effective selection of data structures.
Proceedings of the 32nd ACM SIGPLAN Conference on Programming Language Design and Implementation, 2011

Efficiently speeding up sequential computation through the n-way programming model.
Proceedings of the 26th Annual ACM SIGPLAN Conference on Object-Oriented Programming, 2011

Enriching 3-D Video Games on Multicores.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Parallelizing a Real-Time Physics Engine Using Transactional Memory.
Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011

Work Stealing for Multi-core HPC Clusters.
Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011

Leveraging data-structure semantics for efficient algorithmic parallelism.
Proceedings of the 8th Conference on Computing Frontiers, 2011

2010
An optimization framework for embedded processors with auto-addressing mode.
ACM Trans. Program. Lang. Syst., 2010

Input-driven dynamic execution prediction of streaming applications.
Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2010

Exploiting approximate value locality for data synchronization on multi-core processors.
Proceedings of the 2010 IEEE International Symposium on Workload Characterization, 2010

Dynamic tuning of feature set in highly variant interactive applications.
Proceedings of the 10th International conference on Embedded software, 2010

2009
Editorial: Languages, compilers, and tools for embedded systems.
ACM Trans. Embed. Comput. Syst., 2009

Using Ellipsoidal Domains to Analyze Control Systems Software
CoRR, 2009

2008
Statistically Analyzing Execution Variance for Soft Real-Time Applications.
Proceedings of the Languages and Compilers for Parallel Computing, 2008

2007
Allocating architected registers through differential encoding.
ACM Trans. Program. Lang. Syst., 2007

Power-efficient prefetching for embedded processors.
ACM Trans. Embed. Comput. Syst., 2007

A profile-driven statistical analysis framework for the design optimization of soft real-time applications.
Proceedings of the 6th joint meeting of the European Software Engineering Conference and the ACM SIGSOFT International Symposium on Foundations of Software Engineering, 2007

RSTM : A Relaxed Consistency Software Transactional Memory for Multicores.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006
Parallelizing load/stores on dual-bank memory embedded processors.
ACM Trans. Embed. Comput. Syst., 2006

Using Branch Correlation to Identify Infeasible Paths for Anomaly Detection.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Memory Protection through Dynamic Access Control.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Effective thread management on network processors with compiler analysis.
Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, 2006

Minimizing downtime in seamless migrations of mobile applications.
Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, 2006

Compiler assisted dynamic management of registers for network processors.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

A Scalable Priority Queue Architecture for High Speed Network Processing.
Proceedings of the INFOCOM 2006. 25th IEEE International Conference on Computer Communications, 2006

Compiler Optimizations to Reduce Security Overhead.
Proceedings of the Fourth IEEE/ACM International Symposium on Code Generation and Optimization (CGO 2006), 2006

2005
Performance prediction of large-scale parallel discrete event models of physical systems.
Proceedings of the 37th Winter Simulation Conference, Orlando, FL, USA, December 4-7, 2005, 2005

Differential register allocation.
Proceedings of the ACM SIGPLAN 2005 Conference on Programming Language Design and Implementation, 2005

Efficient application migration under compiler guidance.
Proceedings of the 2005 ACM SIGPLAN/SIGBED Conference on Languages, 2005

Building Intrusion-Tolerant Secure Software.
Proceedings of the 3nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2005), 2005

Anomalous path detection with hardware support.
Proceedings of the 2005 International Conference on Compilers, 2005

An Efficient Frequency Scaling Approach for Energy-Aware Embedded Real-Time Systems.
Proceedings of the Systems Aspects in Organic and Pervasive Computing, 2005

2004
A fast, memory-efficient register allocation framework for embedded systems.
ACM Trans. Program. Lang. Syst., 2004

Balancing register allocation across threads for a multithreaded network processor.
Proceedings of the ACM SIGPLAN 2004 Conference on Programming Language Design and Implementation 2004, 2004

Hardware-managed register allocation for embedded processors.
Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, 2004

Power-efficient prefetching via bit-differential offset assignment on embedded processors.
Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, 2004

A Fast Assembly Level Reverse Execution Method via Dynamic Slicing.
Proceedings of the 26th International Conference on Software Engineering (ICSE 2004), 2004

Static Techniques to Improve Power Efficiency of Branch Predictors.
Proceedings of the High Performance Computing, 2004

Binary translation to improve energy efficiency through post-pass register re-allocation.
Proceedings of the EMSOFT 2004, 2004

Hardware assisted control flow obfuscation for embedded processors.
Proceedings of the 2004 International Conference on Compilers, 2004

HIDE: an infrastructure for efficiently protecting information leakage on the address bus.
Proceedings of the 11th International Conference on Architectural Support for Programming Languages and Operating Systems, 2004

2003
Optimal task scheduling at run time to exploit intra-tile parallelism.
Parallel Comput., 2003

Storage assignment optimizations through variable coalescence for embedded processors.
Proceedings of the 2003 Conference on Languages, 2003

Tamper-resistant whole program partitioning.
Proceedings of the 2003 Conference on Languages, 2003

Compiler Scheduling of Mobile Agents for Minimizing Overheads.
Proceedings of the 23rd International Conference on Distributed Computing Systems (ICDCS 2003), 2003

Method Partitioning - Runtime Customization of Pervasive Programs without Design-time Application Knowledge.
Proceedings of the 23rd International Conference on Distributed Computing Systems (ICDCS 2003), 2003

Optimizing Dynamic Dispatches through Type Invariant Region Analysis.
Proceedings of the High Performance Computing - HiPC 2003, 10th International Conference, 2003

Resolving Register Bank Conflicts for a Network Processor.
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September, 2003

2002
Automatic Compilation of Loops to Exploit Operator Parallelism on Configurable Arithmetic Logic Units.
IEEE Trans. Parallel Distributed Syst., 2002

Loop Restructuring for Data I/O Minimization on Limited On-Chip Memory Embedded Processors.
IEEE Trans. Computers, 2002

Compiler optimizations for Java aglets in distributed data intensive applications.
Proceedings of the 2002 ACM Symposium on Applied Computing (SAC), 2002

Optimizing Static Power Dissipation by Functional Units in Superscalar Processors.
Proceedings of the Compiler Construction, 11th International Conference, 2002

Leakage-proof program partitioning.
Proceedings of the International Conference on Compilers, 2002

A Framework for Parallelizing Load/Stores on Embedded Processors.
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002

2001
Compact and efficient code generation through program restructuringon limited memory embedded DSPs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

A Data Re-use Based Compiler Optimization for FPGAs.
Proceedings of the Field-Programmable Logic and Applications, 2001

A Compilation Method for Communication-Efficient Partitioning of DOALL Loops.
Proceedings of the Compiler Optimizations for Scalable Parallel Systems Languages, 2001

2000
A Framework for Enhancing Code Quality in Limited Register Set Embedded Processors.
Proceedings of the Languages, 2000

A Framework for Efficient Register Allocation through Selective Register Demotion.
Proceedings of the Languages, 2000

Compiler Based Scheduling of Java Mobile Agents.
Proceedings of the Languages and Compilers for Parallel Computing, 2000

A Framework for Loop Distribution on Limited On-Chip Memory Processors.
Proceedings of the Compiler Construction, 9th International Conference, 2000

1999
Storage assignment using expression tree transformations to generate compact and efficient DSP code.
SIGARCH Comput. Archit. News, 1999

Compilation techniques for parallel systems.
Parallel Comput., 1999

A Computation+Communication Load Balanced Loop Partitioning Method for Distributed Memory Systems.
J. Parallel Distributed Comput., 1999

Storage Assignment Optimizations to Generate Compact and Efficient Code on Embedded DSPs.
Proceedings of the 1999 ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI), 1999

Data I/O Minimization for Loops on Limited Onchip Memory Processors.
Proceedings of the Languages and Compilers for Parallel Computing, 1999

Code Restructuring for Improving Real Time Response through Code Speed, Size Trade-offs on Limited Memory Embedded DSPs.
Proceedings of the Languages and Compilers for Parallel Computing, 1999

Efficient Program Partitioning Based on Compiler Controlled Communication.
Proceedings of the Parallel and Distributed Processing, 1999

1998
A Robust Compile Time Method for Scheduling Task Parallelism on Distributed Memory Machines.
J. Supercomput., 1998

A framework for performance-based program partitioning.
Parallel Distributed Comput. Pract., 1998

Compiler Optimizations for Real Time Execution of Loops on Limited Memory Embedded Systems.
Proceedings of the 19th IEEE Real-Time Systems Symposium, 1998

An Efficient Data Partitioning Method for Limited Memory Embedded Systems.
Proceedings of the Languages, 1998

Automatic Analysis of Loops to Exploit Operator Parallelism on Reconfigurable Systems.
Proceedings of the Languages and Compilers for Parallel Computing, 1998

Optimal Task Scheduling to Minimize Inter-Tile Latencies.
Proceedings of the 1998 International Conference on Parallel Processing (ICPP '98), 1998

1996
Program Repartitioning on Varying Communication Cost Parallel Architectures.
J. Parallel Distributed Comput., 1996

Special Issue on Compilation Techniques for Distributed Memory Systems: Guest Editors' Introduction.
J. Parallel Distributed Comput., 1996

A Compile Time Partitioning Method for DOALL Loops on Distributed Memory Systems.
Proceedings of the 1996 International Conference on Parallel Processing, 1996

A Multi-Phase Partitioner and Scheduler for Distributed Memory Systems.
Proceedings of the 29th Annual Hawaii International Conference on System Sciences (HICSS-29), 1996

1995
A Scalable Scheduling Scheme for Functional Parallelism on Distributed Memory Multiprocessor Systems.
IEEE Trans. Parallel Distributed Syst., 1995

Run-time issues in program partitioning on distributed memory systems.
Concurr. Pract. Exp., 1995

A communication+computation load balanced loop partitioning method.
Proceedings of the Seventh IEEE Symposium on Parallel and Distributed Processing, 1995

Classical dependence analysis techniques: sufficiently accurate in practice.
Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995

1994
A Threshold Scheduling Strategy for Sisal on Distributed Memory Machines.
J. Parallel Distributed Comput., 1994

Compiling functional parallelism on distributed-memory systems.
IEEE Parallel Distributed Technol. Syst. Appl., 1994

A Compilation Technique for Varying Communication Cost NUMA Architectures.
Proceedings of the PARLE '94: Parallel Architectures and Languages Europe, 1994

An Empirical Study of the I Test for Exact Data Dependence.
Proceedings of the 1994 International Conference on Parallel Processing, 1994

Compiling Functional Parallelism on a Family of Different Distributed Memory Architectures.
Proceedings of the 1994 International Conference on Parallel Processing, 1994

Scheduling Acyclic Task Graphs on Distributed Memory Parallel Architectures.
Proceedings of the Workshop on Parallel Processing of Discrete Optimization Problems, 1994

1991
A Message Segmentation Technique to Minimize Task Completion Time.
Proceedings of the Fifth International Parallel Processing Symposium, Proceedings, Anaheim, California, USA, April 30, 1991

1990
On Control Flow and Pseudo-Static Dynamic Allocation Strategy.
Proceedings of the 1990 International Conference on Parallel Processing, 1990


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