Santosh Ghosh
Orcid: 0000-0002-7484-1254
According to our database1,
Santosh Ghosh
authored at least 93 papers
between 2007 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
2008
2010
2012
2014
2016
2018
2020
2022
2024
0
5
10
15
4
9
6
3
7
7
3
1
1
2
4
1
3
2
2
3
5
6
1
1
3
2
1
4
3
2
2
5
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
Switch Capacitor-Based Time-Varying Transfer Function for FCN and CNN MLSCA-Resistant AES256 in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024
R-STELLAR: A Resilient Synthesizable Signature Attenuation SCA Protection on AES-256 with built-in Attack-on-Countermeasure Detection.
IACR Cryptol. ePrint Arch., 2024
Exploiting Clock-Slew Dependent Variability in CMOS Digital Circuits Towards Power and EM SCA Resilience.
IACR Cryptol. ePrint Arch., 2024
2023
Improved EM Side-Channel Analysis Attack Probe Detection Range Utilizing Coplanar Capacitive Asymmetry Sensing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023
IEEE Trans. Computers, June, 2023
A novel methodology for the planning of charging infrastructure in the scenario of high EV penetration.
Soft Comput., May, 2023
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023
PG-CAS: Pro-Active EM-SCA Probe Detection Using Switched-Capacitor-Based Patterned-Ground Co-Planar Capacitive Asymmetry Sensing.
IEEE Open J. Circuits Syst., 2023
A 334 μW 0.158 mm<sup>2</sup> ASIC for Post-Quantum Key-Encapsulation Mechanism Saber With Low-Latency Striding Toom-Cook Multiplication.
IEEE J. Solid State Circuits, 2023
A 334µW 0.158mm2 ASIC for Post-Quantum Key-Encapsulation Mechanism Saber with Low-latency Striding Toom-Cook Multiplication Extended Version.
IACR Cryptol. ePrint Arch., 2023
IACR Cryptol. ePrint Arch., 2023
A 334μW 0.158mm<sup>2</sup> ASIC for Post-Quantum Key-Encapsulation Mechanism Saber with Low-latency Striding Toom-Cook Multiplication Authors Version.
CoRR, 2023
Power Side-Channel Vulnerability Assessment of Lightweight Cryptographic Scheme, XOODYAK.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023
Power and EM SCA Resilience in 65nm AES-256 Exploiting Clock-Slew Dependent Variability in CMOS Digital Circuits.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
2022
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022
EM SCA White-Box Analysis-Based Reduced Leakage Cell Design and Presilicon Evaluation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Syn-STELLAR: An EM/Power SCA-Resilient AES-256 With Synthesis-Friendly Signature Attenuation.
IEEE J. Solid State Circuits, 2022
EM-X-DL: Efficient Cross-device Deep Learning Side-channel Attack With Noisy EM Signatures.
ACM J. Emerg. Technol. Comput. Syst., 2022
IACR Cryptol. ePrint Arch., 2022
A 334uW 0.158mm<sup>2</sup> Saber Learning with Rounding based Post-Quantum Crypto Accelerator.
CoRR, 2022
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022
A Digital Cascoded Signature Attenuation Countermeasure with Intelligent Malicious Voltage Drop Attack Detector for EM/Power SCA Resilient Parallel AES-256.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
EM and Power SCA-Resilient AES-256 Through >350× Current-Domain Signature Attenuation and Local Lower Metal Routing.
IEEE J. Solid State Circuits, 2021
Where Star Wars Meets Star Trek: SABER and Dilithium on the Same Polynomial Multiplier.
IACR Cryptol. ePrint Arch., 2021
EM/Power Side-Channel Attack: White-Box Modeling and Signature Attenuation Countermeasures.
IEEE Des. Test, 2021
Proceedings of the SOSP '21: ACM SIGOPS 28th Symposium on Operating Systems Principles, 2021
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021
36.2 An EM/Power SCA-Resilient AES-256 with Synthesizable Signature Attenuation Using Digital-Friendly Current Source and RO-Bleed-Based Integrated Local Feedback and Global Switched-Mode Control.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
PG-CAS: Patterned-Ground Co-Planar Capacitive Asymmetry Sensing for mm-Range EM Side-Channel Attack Probe Detection.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Enhanced Detection Range for EM Side-channel Attack Probes utilizing Co-planar Capacitive Asymmetry Sensing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Int. J. Syst. Assur. Eng. Manag., 2020
J. Cryptogr. Eng., 2020
IACR Cryptol. ePrint Arch., 2020
IACR Cryptol. ePrint Arch., 2020
A >100 Gbps Inline AES-GCM Hardware Engine and Protected DMA Transfers between SGX Enclave and FPGA Accelerator Device.
IACR Cryptol. ePrint Arch., 2020
IEEE Access, 2020
Proceedings of the 14th USENIX Symposium on Operating Systems Design and Implementation, 2020
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
27.3 EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Proceedings of the IEEE Symposium on Computers and Communications, 2020
HCC: 100 Gbps AES-GCM Encrypted Inline DMA Transfers Between SGX Enclave and FPGA Accelerator.
Proceedings of the Information and Communications Security - 22nd International Conference, 2020
Deep Learning Side-Channel Attack Resilient AES-256 using Current Domain Signature Attenuation in 65nm CMOS.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
Practical Approaches Toward Deep-Learning-Based Cross-Device Power Side-Channel Attack.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Lightweight Design-for-Security Strategies for Combined Countermeasures Against Side Channel and Fault Analysis in IoT Applications.
J. Hardw. Syst. Secur., 2019
IACR Cryptol. ePrint Arch., 2019
IACR Cryptol. ePrint Arch., 2019
IEEE Des. Test, 2019
CoRR, 2019
STELLAR: A Generic EM Side-Channel Attack Protection through Ground-Up Root-cause Analysis.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019
2018
ASNI: Attenuated Signature Noise Injection for Low-Overhead Power Side-Channel Attack Immunity.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Ground-up Root-cause Analysis guided Low-Overhead Generic Countermeasure for Electro-Magnetic Side-Channel Attack.
IACR Cryptol. ePrint Arch., 2018
Blindsight: Blinding EM Side-Channel Leakage using Built-In Fully Integrated Inductive Voltage Regulator.
CoRR, 2018
A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
An Evaluation of Lightweight Block Ciphers for Resource-Constrained Applications: Area, Performance, and Security.
J. Hardw. Syst. Secur., 2017
Proceedings of the 38th IEEE Sarnoff Symposium 2017, Newark, NJ, USA, 2017
Proceedings of the Hardware and Architectural Support for Security and Privacy, 2017
High efficiency power side-channel attack immunity using noise injection in attenuated signature domain.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017
2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016
2015
IACR Cryptol. ePrint Arch., 2015
2014
BLAKE-512-Based 128-Bit CCA2 Secure Timing Attack Resistant McEliece Cryptoprocessor.
IEEE Trans. Computers, 2014
Indian thermal power plant challenges and remedies via application of modified data envelopment analysis.
Int. Trans. Oper. Res., 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
2013
Secure Dual-Core Cryptoprocessor for Pairings Over Barreto-Naehrig Curves on FPGA Platform.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013
First-order DPA Vulnerability of Rijndael: Security and Area-delay Optimization Trade-off.
Int. J. Netw. Secur., 2013
2012
J. Cryptogr. Eng., 2012
Proceedings of the Progress in VLSI Design and Test - 16th International Symposium, 2012
Proceedings of the Pairing-Based Cryptography - Pairing 2012, 2012
Differential Scan Attack on AES with X-tolerant and X-masked Test Response Compactor.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012
2011
Petrel: Power and Timing Attack Resistant Elliptic Curve Scalar Multiplier Based on Programmable GF(p) Arithmetic Unit.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
Int. J. Netw. Secur., 2011
IACR Cryptol. ePrint Arch., 2011
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Proceedings of the Security Aspects in Information Technology, 2011
High Speed Cryptoprocessor for η T Pairing on 128-bit Secure Supersingular Elliptic Curves over Characteristic Two Fields.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28, 2011
2010
Proceedings of the Pairing-Based Cryptography - Pairing 2010, 2010
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
2009
IET Inf. Secur., 2009
Parallel crypto-devices for GF(p) elliptic curve multiplication resistant against side channel attacks.
Comput. Electr. Eng., 2009
2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 25th International Conference on Computer Design, 2007
A Speed-Area Optimization of Full Search Block Matching Hardware with Applications in High-Definition TVs (HDTV).
Proceedings of the High Performance Computing, 2007
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007