Santiago Navarro

Orcid: 0000-0003-1868-7288

According to our database1, Santiago Navarro authored at least 4 papers between 2019 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Dual PN Source/Drain Reconfigurable FET for Fast and Low-Voltage Reprogrammable Logic.
IEEE Access, 2020

2019
Simulation Perspectives of Sub-1V Single-Supply Z<sup>2</sup>-FET 1T-DRAM Cells for Low-Power.
IEEE Access, 2019

On the Low-Frequency Noise Characterization of Z<sup>2</sup>-FET Devices.
IEEE Access, 2019

Temperature and Gate Leakage Influence on the Z<sup>2</sup>-FET Memory Operation.
Proceedings of the 49th European Solid-State Device Research Conference, 2019


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